Surface mountable electronic component

• US 10,629,485 B2
• Filed: 09/06/2012
• Issued: 04/21/2020
• Est. Priority Date: 09/06/2011
• Status: Active Grant

• Current Assignee: Vishay Semiconductor GmbH (Vishay Intertechnology Incorporated)
• Original Assignee: Vishay Semiconductor GmbH (Vishay Intertechnology Incorporated)
• Inventors: Mahner, Claus
• Primary Examiner(s): Graybill, David E
• Application Number:
  US14/342,999
• Publication Number:
  US 20140346642A1
• Time in Patent Office: 2,784 Days
• Field of Search: None
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2223/54406 comprising alphanumeric information
• CPC Class Codes: H01L 2223/54473 for use after dicing
• CPC Class Codes: H01L 2224/02379 Fan-out arrangement
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/1451 Function
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/81192 wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 23/3171 the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/14 of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 29/0657 : characterised by the shape of the body
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER

Abstract

A surface mountable electronic component free of connecting wires comprises a semiconductor substrate, wherein a plurality of solderable connection areas are arranged at the underside of the component. The component comprises at least one recess is formed in the region of the edges bounding the underside; and in that the recess is covered with an insulating layer. A method for the manufacture of such a component comprises the formation of corresponding recesses.

Claims

1. A surface mountable electronic component free of connecting wires, having an upper side and an underside, the surface mountable electronic component comprising:

a semiconductor substrate having an upper side surface, an underside surface and four side surfaces, wherein each of the four side surfaces join the underside surface at an edge and are not insulated;

a plurality of planar solderable surfaces formed on the underside of the component;

at least one recess formed in at least a region of the edge, the at least one recess covered with a first insulating layer,

wherein for each at least one recess, a combination of the recess and the first insulating layer forms a hollow groove;

at least one active region formed in a region of the semiconductor structure that is spaced apart from the side surfaces of the semiconductor substrate such that the at least one active region does not contact the hollow groove and the first insulating layer does not completely cover an exposed portion of the at least one active region;

a metallized connection section running directly between the exposed portion of the at least one active area and a downwardly extending metallized connection area;

the connection section at least partially covered by a second insulating layer which covers the connection section with the exception of a contact point between the connection section and the connection area;

the connection area including an upstanding outer side wall; and

the connection area being offset from the at least one active area.

2. A component in accordance with claim 1, wherein

the plurality of solderable surfaces are formed exclusively on the underside of the component.

3. A component in accordance with claim 1, wherein a maximum depth of the recess amounts to at least 5 μ

m and at most 40 μ

m.

4. A component in accordance with claim 1, wherein

a maximum depth of the recess amounts to at least 2% and at most 10% of a height of the component.

5. A component in accordance with claim 1,

wherein the recess has a maximum depth that is equal to, or less than, a width of the recess.

6. A component in accordance with claim 1,

wherein

the first insulating layer comprises at least one of silicon oxide, silicon nitride, paint or an adhesive.

7. A component in accordance with claim 1,

wherein

the thickness of the first insulating layer amounts to less than 2 μ

m.

8. A component in accordance with claim 3, wherein the maximum depth of the recess amounts to approximately 10 to 15 μ

m.

9. A component in accordance with claim 4,

wherein the maximum depth of the recess amounts to between approximately 3% to 6% of the height of the component.

10. A component in accordance with claim 1,

wherein the thickness of the first insulating layer amounts to less than 1 μ

m.

15. The surface mountable electronic component of claim 1, wherein the outer side wall of the connection area is positioned more outwardly toward at least one of the side surfaces of the semiconductor substrate than the at least one active area.

11. A surface mountable electronic component free of connecting wires, having an upper side and an underside, the surface mountable electronic component comprising:

a semiconductor substrate having an upper side surface, an underside surface and four side surfaces, wherein each of the four side surfaces join the underside surface at an edge and are not insulated;

a plurality of solderable surfaces formed on the underside of the component; and

at least one recess formed in at least a region of the edge, the at least one recess covered with a first insulating layer,

wherein for each at least one recess, a combination of the recess and the first insulating layer forms a shape including;

a planar shoulder section, the planar shoulder section being inclined with respect to a plane defined by the underside of the surface mountable electronic component, and

a base section bounding the inclined shoulder section on one side and a side surface of the semiconductor substrate at the other side; and

at least one active region formed in a region of the semiconductor structure that is spaced apart from the side surfaces of the semiconductor substrate such that the at least one active region does not contact the at least one recess and the first insulating layer does not completely cover an exposed portion of the at least one active region;

a metallized connection section running directly between the exposed portion of the at least one active area and a downwardly extending metallized connection area;

the connection section at least partially covered by a second insulating layer which covers the connection section with the exception of a contact point between the connection section and the connection area;

the connection area including an upstanding outer side wall; and

the connection area being offset from the at least one active area.

12. The surface mountable electronic component of claim 11,

wherein a degree of inclination of the planar shoulder section with respect to the plane amounts to 30°

to 80°

.

13. The surface mountable electronic component of claim 11,

wherein a degree of inclination of the planar shoulder section with respect to the plane amounts to approximately 60°

.

14. The surface mountable electronic component of claim 11,

wherein the base section runs in parallel to the plane defined by the underside of the surface mountable electronic component.

16. The surface mountable electronic component of claim 11, wherein the outer side wall of the connection area is positioned more outwardly toward at least one of the side surfaces of the semiconductor substrate than the at least one active area.