Semiconductor package and method for fabricating the same

• US 10,629,522 B2
• Filed: 06/06/2019
• Issued: 04/21/2020
• Est. Priority Date: 02/08/2017
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Shih, Shing-Yih
• Primary Examiner(s): Toledo, Fernando L
• Assistant Examiner(s): Prasad, Neil R
• Application Number:
  US16/433,426
• Publication Number:
  US 20190287889A1
• Time in Patent Office: 320 Days
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/16238 the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/81005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/3135 Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/5383 : Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5385 : Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect

Abstract

A semiconductor package including at least one semiconductor device, a first redistribution layer, a first molding compound, a second molding compound, conductive vias and a second redistribution layer. The first redistribution layer is disposed beneath the semiconductor device and electrically connected to the semiconductor device. The first molding compound is disposed over the first redistribution layer and surrounds the semiconductor device. The second molding compound surrounds the first redistribution layer and at least a part of the first molding compound. The conductive vias extend through the second molding compound. The second redistribution layer is disposed on a surface of the second molding compound away from the first redistribution layer. The second redistribution layer is electrically connected to the first redistribution layer through the conductive vias.

Claims

1. A semiconductor package comprising:

a first semiconductor device;

a second semiconductor device having at least one surface being coplanar with a surface of the first semiconductor device;

a first redistribution layer disposed beneath the first semiconductor device and second semiconductor device and electrically connected to the first semiconductor device and the second semiconductor device;

a first molding compound disposed over the first redistribution layer and surrounding the first semiconductor device and second semiconductor device;

a second molding compound surrounding the first redistribution layer and at least a part of the first molding compound;

conductive vias extending through the second molding compound; and

a second redistribution layer disposed beneath a surface of the second molding compound away from the first redistribution layer and electrically connected to the first redistribution layer through the conductive vias.

2. The semiconductor package of claim 1, wherein the first redistribution layer comprises:

a first dielectric layer; and

first discrete conductive routes extending through the first dielectric layer, wherein at least one conductive route of the first discrete conductive routes extends between and connects the first semiconductor device to the second semiconductor device.

3. The semiconductor package of claim 2, wherein the first redistribution layer further comprises a second dielectric layer in contact with the first dielectric layer and wherein the first discrete conductive routes extend through the second dielectric layer.

4. The semiconductor package of claim 2, where in the first dielectric layer is in direct contact with the first molding compound.

5. The semiconductor package of claim 1, wherein at least a portion of the first molding compound is disposed between the first semiconductor device and the first redistribution layer and abuts against the first redistribution layer.

6. The semiconductor package of claim 1, further comprising an additional dielectric layer disposed on a surface of the first redistribution layer opposite the first molding compound, wherein the conductive vias extend through the additional dielectric layer.

7. The semiconductor package of claim 6, wherein at least one of a dielectric coefficient of the additional dielectric layer, a dielectric coefficient of the first redistribution layer, or a dielectric coefficient of the second redistribution layer is different from the others of the dielectric coefficients.

8. The semiconductor package of claim 1, wherein a glass transition temperature of the first molding compound is greater than a glass transition temperature of the second molding compound.

9. The semiconductor package of claim 1, wherein a smallest pitch width of the first redistribution layer is distinct from a smallest pitch width of the second redistribution layer.

10. The semiconductor package of claim 1, wherein the surface of the first semiconductor device, the at least one surface of the second semiconductor device, a surface of the first molding compound, and a surface of the second molding compound facing away from the second redistribution layer are coplanar.

11. The semiconductor package of claim 1, further comprising conductive bumps extended through the first molding compound and electrically connecting the first redistribution layer to both the first semiconductor device and the second semiconductor device.

12. The semiconductor package of claim 1, further comprising solder balls disposed on a surface of the second redistribution layer opposite the second molding compound.

13. The semiconductor package of claim 1, wherein the first redistribution layer is partially encapsulated by the first molding compound and partially encapsulated by the second molding compound.

14. A method for fabricating a semiconductor package comprising:

providing a workpiece, wherein the workpiece comprising a first redistribution layer, conductive vias and a first wafer, the conductive vias are extended into the first wafer, the first redistribution layer being disposed on the first wafer, connected to the conductive vias, and comprising first discrete conductive routes formed therein;

disposing a first semiconductor device on a side of the first redistribution layer away from the conductive vias;

disposing a second semiconductor device on the side of the first redistribution layer away from the conductive vias, the redistribution layer being electrically connected to the first semiconductor device and the second semiconductor device, wherein the second semiconductor device has at least one surface coplanar with a surface of the first semiconductor device;

forming a first molding compound to at least partially surround the first semiconductor device and the second semiconductor device removing the first wafer;

forming a second molding compound to surround the first redistribution layer and at least part of the first molding compound, wherein the conductive vias are exposed on a surface of the second molding compound away from the first redistribution layer; and

forming a second redistribution layer on a surface of the second molding compound away from the first redistribution layer and electrically connected to the first redistribution layer through the conductive vias.

15. The method of claim 14, wherein forming the first molding compound further comprises disposing at least a portion of the first molding compound between the first semiconductor device and the first redistribution layer, the first molding compound abutting against the first redistribution layer.

16. The method of claim 14, wherein disposing the second semiconductor device on the side of the first redistribution layer comprises disposing the second semiconductor device such that first discrete conductive routes extend between and connect the first semiconductor device to the second semiconductor device.

17. The method of claim 14, further comprising:

depositing a dielectric layer on the first wafer;

forming trenches extending through the dielectric layer and extending into the first wafer; and

filling the trenches with a conductive material to form the conductive vias.

18. The method of claim 14, further comprising singulating the first and second semiconductor devices through the first molding compound and the first redistribution layer.

19. The method of claim 14, further comprising singulating through the first molding compound and the first redistribution layer to separate the first semiconductor device from the second semiconductor device.

20. A semiconductor package comprising:

a first semiconductor device;

a second semiconductor device;

a first redistribution layer disposed beneath the first semiconductor device and second semiconductor device and electrically connected to the first semiconductor device and the second semiconductor device, wherein the first redistribution layer comprises;

a dielectric layer; and

discrete conductive routes extending through the dielectric layer, wherein at least one conductive route of the discrete conductive routes extends between and connects the first semiconductor device to the second semiconductor device;

a first molding compound disposed over the first redistribution layer and surrounding the first semiconductor device and second semiconductor device;

a second molding compound surrounding the first redistribution layer and at least a part of the first molding compound; and

a second redistribution layer disposed beneath a surface of the second molding compound opposite the first redistribution layer and electrically connected to the first redistribution layer.