Power island segmentation for selective bond-out

• US 10,629,533 B2
• Filed: 03/13/2018
• Issued: 04/21/2020
• Est. Priority Date: 03/13/2018
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Inventors: Kerr, Benjamin
• Primary Examiner(s): Muse, Ismail A
• Application Number:
  US15/920,002
• Publication Number:
  US 20190287906A1
• Time in Patent Office: 770 Days
• CPC Class Codes: H01L 2224/06131 being uniform, i.e. having a uniform pitch across the array
• CPC Class Codes: H01L 2224/06132 being non uniform, i.e. having a non uniform pitch across the array
• CPC Class Codes: H01L 2224/06134 covering only portions of the surface to be connected
• CPC Class Codes: H01L 2224/06164 covering only portions of the surface to be connected
• CPC Class Codes: H01L 2224/06177 Combinations of arrays with different layouts
• CPC Class Codes: H01L 23/49 wire-like arrangements or pins or rods using optical fibres H01L23/48; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas

Abstract

A semiconductor chip includes a semiconductor die formed on a substrate, a first power mesh formed on the substrate, and a second power mesh formed on the substrate electrically isolated from the first power mesh. The semiconductor chip also includes a first circuit block formed on the substrate and electrically connected to the first power mesh, and a second circuit block formed on the substrate and electrically connected to the second power mesh. The first circuit block and the second circuit block are communicatively coupled to a first plurality of external circuit connections and a second plurality of external circuit connections, respectively. The semiconductor chip also includes one or more first signal pins and one or more second signal pins formed on the substrate, the first and second signal pins designed to receive external signals.

Claims

1. A semiconductor chip comprising a semiconductor die formed on a substrate, the semiconductor die comprising:

a first power mesh formed on the substrate;

a second power mesh formed on the substrate and configured to be electrically isolated from the first power mesh;

a first circuit block formed on the substrate and electrically connected to the first power mesh configured to supply power to the first circuit block;

a second circuit block formed on the substrate and electrically connected to the second power mesh configured to supply power to the second circuit block;

a first plurality of external circuit connections communicatively coupled to the first circuit block and communicatively isolated from the second circuit block;

a second plurality of external circuit connections communicatively coupled to the second circuit block and communicatively isolated from the first circuit block;

one or more first signal pins formed on the substrate configured to be communicatively coupled to receive first one or more signals external to the semiconductor chip; and

one or more second signal pins formed on the substrate configured to be communicatively coupled to receive second one or more signals external to the semiconductor chip;

wherein the first power mesh is formed over the first circuit block, and the second power mesh is formed over the second circuit block.

2. The semiconductor chip of claim 1, wherein the second circuit block is configured to be non-operational.

3. The semiconductor chip of claim 2, wherein the first circuit block is coupled to at least one of the one or more first signal pins and at least one of the one or more second signal pins.

4. The semiconductor chip of claim 3, wherein the second circuit block is coupled to at least one of the one or more second signal pins and is not coupled to any of the one or more first signal pins.

5. The semiconductor chip of claim 4, wherein the one or more first signal pins are configured to receive power from a power supply and the one or more second signal pins are configured to receive a ground supply.

6. The semiconductor chip of claim 5, wherein the second power mesh does not receive power from the power supply.

7. The semiconductor chip of claim 4, wherein the first power mesh is segmented by providing a first layer of connections configured to connect to a ground supply and a second layer of connections configured to connect to a power supply, and the second power mesh is segmented by providing a third layer of connections configured to connect to the ground supply and a fourth layer of connections configured to connection to the power supply.

8. The semiconductor chip of claim 7, wherein signal pins connected to the third layer and the fourth layer are not coupled to the power supply.

9. The semiconductor of claim 8, wherein the signal pins connected to the third layer and the fourth layer are coupled to a ground supply.

10. The semiconductor chip of claim 1, wherein a flow of current through the first circuit block does not induce a leakage current in the second circuit block.

11. The semiconductor chip of claim 1, wherein the first circuit block and second circuit block are instantiated on a ball grid array.

12. The semiconductor chip of claim 11, wherein the second circuit block is connected to a ground supply by a plurality of ball connections.

13. The semiconductor chip of claim 1, further comprising a plurality of external devices coupled to the first plurality of external circuit connections.

14. The semiconductor chip of claim 1, wherein the first plurality of external circuit connections are physically isolated from the second circuit block and the second plurality of external circuit connections are physically isolated from the first circuit block.