Package structure and manufacturing method thereof

• US 10,629,554 B2
• Filed: 04/13/2018
• Issued: 04/21/2020
• Est. Priority Date: 04/13/2018
• Status: Active Grant

• Current Assignee: Powertech Technology Inc
• Original Assignee: Powertech Technology Inc
• Inventors: Lin, Nan-Chun, Hsu, Hung-Hsin
• Primary Examiner(s): Fan, Bo
• Application Number:
  US15/952,261
• Publication Number:
  US 20190319000A1
• Time in Patent Office: 739 Days
• Field of Search: 257773
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2221/68372 used to support a device or wafer when forming electrical connections thereto
• CPC Class Codes: H01L 2224/02245 Flow barrier
• CPC Class Codes: H01L 2224/02255 Shape of the auxiliary member
• CPC Class Codes: H01L 2224/0226 Material of the auxiliary member
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02379 Fan-out arrangement
• CPC Class Codes: H01L 2224/02381 Side view
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/2413 Connecting within a semiconductor or solid-state body
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/3171 the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 23/3185 the coating covering also the sidewalls of the semiconductor body
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2924/1816 : Exposing the passive side of the semiconductor or solid-state body
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect

Abstract

A package structure includes a die, an encapsulant, a dam structure, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The encapsulant encapsulates sidewalls of the die. The encapsulant has a first surface and a second surface opposite to the first surface. The first surface is coplanar with the rear surface of the die. The second surface is located at a level height different from the active surface of the die. The dam structure is disposed on the active surface of the die. A top surface of the dam structure is substantially coplanar with the second surface of the encapsulant. The redistribution structure is over the encapsulant, the dam structure, and the die. The redistribution structure is electrically connected to the die.

Claims

1. A package structure, comprising:

a die having an active surface and a rear surface opposite to the active surface;

an encapsulant encapsulating sidewalls of the die, wherein the encapsulant has a first surface and a second surface opposite to the first surface, the first surface is coplanar with the rear surface of the die, and the second surface is located at a level height different from the active surface of the die;

a dam structure disposed on the active surface of the die, wherein a top surface of the dam structure is substantially coplanar with the second surface of the encapsulant; and

a redistribution structure over the encapsulant, the dam structure, and the die, wherein the redistribution structure is electrically connected to the die,

wherein the dam structure is spaced apart from a conductive element of the redistribution structure, the die comprises a plurality of connection pads and the dam structure comprises at least one opening, and the at least one opening exposes the plurality of connection pads, and the dam structure comprises a ring pattern having one opening, the ring pattern is disposed along edges of the active surface within the die, and the one opening exposes the plurality of connection pads.

2. The package structure according to claim 1, further comprising a plurality of conductive terminals over the redistribution structure.

3. The package structure according to claim 1, wherein a thickness of the encapsulant is larger than a thickness of the die.

4. The package structure according to claim 1, wherein a sum of a thickness of the die and a thickness of the dam structure is equal to a thickness of the encapsulant.

5. The package structure according to claim 1, wherein the redistribution structure is directly in contact with the plurality of connection pads.

6. The package structure according to claim 1, wherein a material of the dam structure comprises photosensitive material, epoxy, polyimide, silicone based material, or a combination thereof.

7. The package structure according to claim 1, wherein the rear surface of the die is exposed by the encapsulant.