Direct-bonded LED arrays and applications

• US 10,629,577 B2
• Filed: 03/13/2018
• Issued: 04/21/2020
• Est. Priority Date: 03/16/2017
• Status: Active Grant

• Current Assignee: Adeia Semiconductor Technologies LLC (Adeia Inc.)
• Original Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Inventors: Tao, Min, Wang, Liang, Katkar, Rajesh, Uzoh, Cyprian Emeka
• Primary Examiner(s): Pham, Hoai V
• Application Number:
  US15/919,570
• Publication Number:
  US 20190088633A1
• Time in Patent Office: 770 Days
• CPC Class Codes: H01L 21/02118 carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC polymers per se C08G, photoresist per se G03F
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 2224/08137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/08145 the bodies being stacked
• CPC Class Codes: H01L 2224/80013 Plasma cleaning
• CPC Class Codes: H01L 2224/80355 having an external coating, e.g. protective bond-through coating
• CPC Class Codes: H01L 2224/80357 being flush with the surface
• CPC Class Codes: H01L 24/08 of an individual bonding area
• CPC Class Codes: H01L 24/80 Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/167 comprising optoelectronic devices, e.g. LED, photodiodes
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/156 two-dimensional arrays
• CPC Class Codes: H01L 2933/0016 relating to electrodes
• CPC Class Codes: H01L 2933/0025 relating to coatings
• CPC Class Codes: H01L 2933/0066 relating to arrangements for conducting electric current to or from the semiconductor body
• CPC Class Codes: H01L 33/007 comprising nitride compounds
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/06 within the light emitting region, e.g. quantum confinement structure or tunnel barrier
• CPC Class Codes: H01L 33/32 : containing nitrogen
• CPC Class Codes: H01L 33/44 : characterised by the coatings, e.g. passivation layer or anti-reflective coating
• CPC Class Codes: H01L 33/46 : Reflective coating, e.g. dielectric Bragg reflector
• CPC Class Codes: H01L 33/62 : Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

Direct-bonded LED arrays and applications are provided. An example process fabricates a LED structure that includes coplanar electrical contacts for p-type and n-type semiconductors of the LED structure on a flat bonding interface surface of the LED structure. The coplanar electrical contacts of the flat bonding interface surface are direct-bonded to electrical contacts of a driver circuit for the LED structure. In a wafer-level process, micro-LED structures are fabricated on a first wafer, including coplanar electrical contacts for p-type and n-type semiconductors of the LED structures on the flat bonding interface surfaces of the wafer. At least the coplanar electrical contacts of the flat bonding interface are direct-bonded to electrical contacts of CMOS driver circuits on a second wafer. The process provides a transparent and flexible micro-LED array display, with each micro-LED structure having an illumination area approximately the size of a pixel or a smallest controllable element of an image represented on a high-resolution video display.

Claims

1. An apparatus, comprising:

a first dielectric bonding surface of a first wafer comprising a light emitting diode (LED) array;

a second dielectric bonding surface of a second wafer comprising CMOS driver circuits, one CMOS driver circuit aligned on the second wafer for each LED element of the LED array on the first wafer, each CMOS driver circuit to make a corresponding LED element individually controllable;

coplanar conductive areas on the first dielectric bonding surface of the first wafer comprising electrical contacts of each respective LED element, wherein the coplanar conductive areas are within a horizontal planar footprint of the respective LED element;

coplanar conductive areas on the second dielectric bonding surface of the second wafer comprising electrical contacts of each respective CMOS driver, wherein the coplanar conductive areas are within a horizontal planar footprint of a corresponding LED element of the first wafer;

oxide-to-oxide direct bonds between dielectric areas of the first bonding surface of the first wafer and the second bonding surface of the second wafer, and

metal-to-metal direct bonds between corresponding coplanar conductive areas of the first bonding surface of the first wafer and the second bonding surface of the second wafer.

2. The apparatus of claim 1, wherein the coplanar conductive areas comprise:

first coplanar conductive areas for electrical contact to an n-type layer of a group III-V semiconductor of each LED element; and

second coplanar conductive areas for electrical contact to a p-type layer of a group III-V semiconductor of each LED element.

3. The apparatus of claim 2, wherein the first coplanar conductive areas comprise multiple conductive contacts to the n-type layer of a single LED element, and the second coplanar conductive areas comprise multiple conductive contacts to the p-type layer of the single LED element.

4. The apparatus of claim 2, further comprising a frame-traced dot array electrode as the electrical contact to the n-type layer of the group III-V semiconductor of each LED element;

and

a circular or square dot array electrode as the electrical contact to the p-type layer of the group III-V semiconductor of each LED element.

5. The apparatus of claim 1, further comprising at least a third coplanar conductive area electrically isolated from the first conductive area and the second conductive area, the third coplanar conductive area for thermal dissipation, for connecting to an electrical ground, or for conducting a signal.

6. The apparatus of claim 1, wherein each LED element in the LED array of the first wafer comprises a micro-LED having an illumination area approximately a size of a pixel of a high-resolution video display, or an illumination area approximately a size of a smallest controllable element of an image represented on the high-resolution video display;

and

wherein each micro-LED is individually controlled by its corresponding CMOS driver on the second wafer.

7. The apparatus of claim 1, wherein each oxide-to-oxide direct bond between dielectric areas of the first bonding surface of the first wafer and the second bonding surface of the second wafer comprises at least one plasma-activated surface of the oxide-to-oxide direct bond.

8. The apparatus of claim 1, further comprising a thinned or a flexible organic substrate of the first wafer and a thinned or a flexible organic substrate of the second wafer providing a flexible and transparent LED array display.

9. The apparatus of claim 1, further comprising a distributed Bragg reflector (DBR) located at a top of each LED element, or at a bottom of each LED element, or at both a top and a bottom of each LED element.

10. The apparatus of claim 1, further comprising an optical waveguide bonded to a top surface or a side surface of the LED array.

11. The apparatus of claim 1, further comprising a semiconductor element bonded to a top surface or a side surface of the LED array.

12. An apparatus, comprising:

micro-LED structures of an LED array fabricated on a first wafer, each micro-LED structure comprising a single micro-LED;

a flat bonding surface of the first wafer including, for each single micro-LED, a first coplanar electrical contact for a p-type semiconductor of the single micro-LED and a second coplanar electrical contact for an n-type semiconductor of the single micro-LED;

wherein the first coplanar electrical contact and the second coplanar electrical contact of each single micro-LED are within a horizontal planar footprint of the single micro-LED;

a corresponding CMOS driver circuit for each single micro-LED, each corresponding CMOS driver circuit fabricated on a second wafer;

a flat bonding surface of the second wafer including, for each corresponding CMOS driver circuit, a first coplanar electrical contact for electrical connection to the p-type semiconductor of the corresponding single micro-LED of the first wafer and a second coplanar electrical contact for electrical connection to the n-type semiconductor of the corresponding single micro-LED of the first wafer;

an oxide-to-oxide direct bond between dielectric parts of the flat bonding surfaces of the first wafer and the second wafer; and

metal-to-metal direct bonds between respective first coplanar electrical contacts of the first wafer and the second wafer, and metal-to-metal direct bonds between respective second coplanar electrical contacts of the first wafer and the second wafer.

13. The apparatus of claim 12, wherein a horizontal planar footprint of each single micro-LED is adjacent and contiguous with horizontal planar footprints of neighboring micro-LEDs of the LED array;

and

wherein each single micro-LED and its corresponding CMOS driver circuit comprise a smallest controllable element for displaying an image on the LED array.

14. The apparatus of claim 13, wherein the smallest controllable element is only a part of a single pixel for displaying the image.