Power semiconductor device having different gate crossings, and method for manufacturing thereof

• US 10,629,595 B2
• Filed: 06/27/2018
• Issued: 04/21/2020
• Est. Priority Date: 06/29/2017
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Ouvrard, Cedric, Braz, Cesar Augusto, Guillemant, Olivier, Laforet, David, Noebauer, Gerhard, Yip, Li Juin
• Primary Examiner(s): Yasmeen, Nishath
• Application Number:
  US16/020,133
• Publication Number:
  US 20190006357A1
• Time in Patent Office: 664 Days
• Field of Search: None
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0834 Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/417 carrying the current to be rectified, amplified or switched
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7396 with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A power semiconductor device includes a semiconductor substrate having a first side. A plurality of active transistor cells is formed in an active area of the semiconductor substrate. Each of the plurality of active transistor cells includes a spicular trench which extends from the first side into the semiconductor substrate and has a field electrode. A gate electrode structure has a plurality of intersecting gate trenches running between the spicular trenches. The intersecting gate trenches form gate crossing regions of different shape when seen in a plan projection onto the first side of the power semiconductor device.

Claims

1. A power semiconductor device, comprising:

a semiconductor substrate having a first side;

a plurality of active transistor cells formed in an active area of the semiconductor substrate, each of the plurality of active transistor cells comprising a spicular trench which extends from the first side into the semiconductor substrate and comprises a field electrode; and

a gate electrode structure comprising a plurality of intersecting gate trenches running between the spicular trenches,

wherein the plurality of intersecting gate trenches comprises a plurality of first gate crossing regions and a plurality of second gate crossing regions, each of the first gate crossing regions comprising a first wall section, each of the second gate crossing regions comprising a second wall section,

wherein the first wall section forms a transition that joins two transverse gate trench spans together,

wherein the second wall section forms a transition that joins two transverse gate trench spans together,

wherein when seen in a plan projection onto the first side of the semiconductor substrate, the first wall section has a first radius and the second wall section has a second radius that is different from the first radius.

2. The power semiconductor device of claim 1, wherein, when seen in the plan projection onto the first side, each of the first gate crossing regions defines a round transition between intersecting gate trenches with the first radius and each of the second gate crossing regions defines a sharp transition between intersecting gate trenches with the second radius, the sharp transition being relatively sharper in comparison to the round transition.

3. The power semiconductor device of claim 2, wherein the first radius is at least twice as large as the second radius.

4. The power semiconductor device of claim 2, wherein a total number of the first gate crossing regions between intersecting gate trenches is equal to or higher than a total number of the second gate crossing regions between intersecting gate trenches in the active area.

5. The power semiconductor device of claim 2, wherein a total number of the first gate crossing regions between intersecting gate trenches is between 50% and 90% of a total number of the first gate crossing regions and the second gate crossing regions in the active area.

6. The power semiconductor device of claim 2, wherein a total number of the first gate crossing regions between intersecting gate trenches is between 60% and 80% of a total number of the first gate crossing regions and the second gate crossing regions in the active area.

7. The power semiconductor device of claim 2, wherein the gate crossing regions further comprises third gate crossing regions, wherein, when seen in the plan projection onto the first side, each of third gate crossing regions defines a round transition between intersecting gate trenches with a third radius, and wherein the third radius is smaller than the first radius and larger than the second radius.

8. The power semiconductor device of claim 1, wherein the gate electrode structure comprises a gate dielectric between a gate electrode and the semiconductor substrate, and wherein the gate dielectric has substantially the same thickness in the gate crossing regions of different shape.

9. The power semiconductor device of claim 1, wherein each active transistor cell comprises a body region and a gate electrode in a respective gate trench of the gate electrode structure.

10. The power semiconductor device of claim 1, wherein the second gate crossing defines a local threshold voltage having an absolute value which is about 60% to 80% of an absolute value of a local threshold voltage of the first gate crossings.

11. A power semiconductor device, comprising:

a semiconductor substrate having a first side and an active area;

a plurality of spaced apart spicular trenches in the active area and extending from the first side into the semiconductor substrate, each of the spicular trenches comprising a field electrode; and

a plurality of intersecting gate trenches between adjacent spicular trenches,

wherein, when seen in a plan projection onto the first side, the plurality of the intersecting gate trenches form a grid structure with a plurality of grid meshes to surround respective spicular trenches,

wherein the gate trenches comprise respective gate electrodes, are adjacent to body regions and define channel regions in the body regions,

wherein a respective channel region completely surrounds a respective spicular trench when seen in the plan projection onto the first side of the semiconductor substrate,

wherein at a first one of the grid meshes, a first wall section of the gate trenches joins transverse spans of the gate trenches together,

wherein at a second one of the grid meshes, a second wall section of the gate trenches joins transverse spans of the gate trenches together,

wherein the wall section has a different shape as the second wall section when seen in plan projection onto the first side, and

wherein the plurality of grid meshes comprises first grid meshes having a substantially round boundary and second grid meshes having a partially straight boundary, wherein a percentage ratio of straight span length to curved span length in an enclosed boundary formed by the first grid meshes is greater than a percentage ratio of straight span length to curved span length formed by the second grid meshes.

12. The power semiconductor device of claim 11, wherein a total number of the first grid meshes is equal to or higher than a total number of the second grid meshes in the active area.

13. The power semiconductor device of claim 11, wherein a total number of the first grid meshes is between 50% and 90% of a total number of the first grid meshes and the second grid meshes in the active area.

14. The power semiconductor device of claim 11, wherein a total number of the first grid meshes is between 60% and 80% of a total number of the first grid meshes and the second grid meshes in the active area.