Memory device having electrically floating body transistor

• US 10,629,599 B2
• Filed: 12/18/2018
• Issued: 04/21/2020
• Est. Priority Date: 04/08/2012
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Widjaja, Yuniarto, Han, Jin-Woo, Louie, Benjamin S.
• Primary Examiner(s): Crawford, Latanya N
• Application Number:
  US16/224,534
• Publication Number:
  US 20190148381A1
• Time in Patent Office: 490 Days
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: H01L 29/0804 Emitter regions of bipolar transistors
• CPC Class Codes: H01L 29/0821 Collector regions of bipolar transistors
• CPC Class Codes: H01L 29/1004 Base region of bipolar transistors
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/70 Bipolar devices
• CPC Class Codes: H01L 29/73 Bipolar junction transistors
• CPC Class Codes: H01L 29/7302 structurally associated with other devices assemblies of devices H01L25/00; integrated circuits H01L27/00; IGBT H01L29/7393
• CPC Class Codes: H01L 29/732 Vertical transistors
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H10B 12/10 DRAM devices comprising bipolar components
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND

Abstract

A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states. A first region of the memory cell is in electrical contact with the floating body region. A second region of the memory cell is spaced apart from the first region and is also in electrical contact with the floating body region. A gate is positioned between the first and second regions. A back-bias region is configured to generate impact ionization when the memory cell is in one of the first and second states, and the back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of the first and second states.

Claims

1. A semiconductor memory cell comprising:

a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states; and

a back bias region;

wherein said floating body region acts as a base region of a first bipolar transistor that maintains the state of said memory cell;

wherein said back-bias region acts as a collector region of said first bipolar transistor and has a lower band gap than said floating body region;

wherein said floating body region acts as a base region of a second bipolar transistor that is used to perform at least one of reading and writing the state of said memory cell; and

wherein current flow through said second bipolar transistor is larger when said memory cell is in one of said first and second states than when said memory cell is in the other of said first and second states.

2. The semiconductor memory cell of claim 1, further comprising a gate region positioned above said floating body region.

3. The semiconductor memory cell of claim 1, wherein said back-bias region is configured to maintain a charge in said floating body region.

4. The semiconductor memory cell of claim 1, wherein said first and second states are stable states.

5. The semiconductor memory cell of claim 1, wherein a product of forward emitter gain and impact ionization efficiency of said first bipolar transistor approaches unity when said memory cell is in one of said first and second states, and wherein impact ionization, when said memory cell is in the other of said first and second states is less than the impact ionization when said memory cell is in said one of said first and second states.

6. The semiconductor memory cell of claim 1, wherein said memory cell states are maintained through impact ionization.

7. The semiconductor memory cell of claim 1, wherein said semiconductor memory cell is formed in a fin structure.

8. A semiconductor memory array comprising:

a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell includes;

a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states; and

a back bias region;

wherein said floating body region acts as a base region of a first bipolar transistor that maintains the state of said memory cell;

wherein said back-bias region acts as a collector region of said first bipolar transistor and has a lower band gap than said floating body region;

wherein said floating body region acts as a base region of a second bipolar transistor that is used to perform at least one of reading and writing the state of said memory cell; and

wherein current flow through said second bipolar transistor is larger when said memory cell is in one of said first and second states than when said memory cell is in the other of said first and second states;

wherein said back bias region is commonly connected to at least two of said memory cells.

9. The semiconductor memory array of claim 8, wherein each of said semiconductor memory cells further comprises a gate region positioned above said floating body region.

10. The semiconductor memory array of claim 8, wherein said back-bias region is configured to maintain a charge in said floating body region.

11. The semiconductor memory array of claim 8, wherein said first and second states are stable states.

12. The semiconductor memory array of claim 8, wherein a product of forward emitter gain and impact ionization efficiency of said first bipolar transistor approaches unity when said memory cell is in one of said first and second states, and wherein impact ionization, when said memory cell is in the other of said first and second states is less than the impact ionization when said memory cell is in said one of said first and second states.

13. The semiconductor memory array of claim 8, wherein said memory cell states are maintained through impact ionization.

14. The semiconductor memory array of claim 8, wherein said semiconductor memory cells are formed in at least one fin structure.

15. An integrated circuit comprising:

a semiconductor memory array comprising;

a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell includes;

a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states; and

a back bias region;

wherein said floating body region acts as a base region of a first bipolar transistor that maintains the state of said memory cell;

wherein said back-bias region acts as a collector region of said first bipolar transistor and has a lower band gap than said floating body region;

wherein said floating body region acts as a base region of a second bipolar transistor that is used to perform at least one of reading and writing the state of said memory cell;

wherein current flow through said second bipolar transistor is larger when said memory cell is in one of said first and second states than when said memory cell is in the other of said first and second states;

wherein said back bias region is commonly connected to at least two of said memory cells; and

a control circuit configured to provide electrical signals to said back bias region.

16. The integrated circuit of claim 15, wherein each of said semiconductor memory cells further comprises a gate region positioned above said floating body region.

17. The integrated circuit of claim 15, wherein said back-bias region is configured to maintain a charge in said floating body region.

18. The integrated circuit of claim 15, wherein said first and second states are stable states.

19. The integrated circuit of claim 15, wherein said memory cell states are maintained through impact ionization.

20. The integrated circuit of claim 15, wherein at least one of said semiconductor memory cells is formed in a fin structure.