Transistor and capacitor structures for analog memory neural network

• US 10,629,601 B2
• Filed: 07/11/2018
• Issued: 04/21/2020
• Est. Priority Date: 07/11/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Leobandung, Effendi
• Primary Examiner(s): Tobergte, Nicholas J
• Application Number:
  US16/032,770
• Publication Number:
  US 20200020695A1
• Time in Patent Office: 650 Days
• CPC Class Codes: G06N 3/065 Analogue means
• CPC Class Codes: G06N 3/08 Learning methods
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 28/90 having vertical extensions
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/01 Manufacture or treatment
• CPC Class Codes: H10B 12/03 Making the capacitor or connections thereto
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND

Abstract

A method for manufacturing a semiconductor device includes forming a plurality of transistors on a semiconductor substrate. The formation of the plurality of transistors includes recessing channels of at least two transistors of the plurality of transistors. In the method, a stacked capacitor is formed on the semiconductor substrate, and the stacked capacitor is electrically connected in parallel to the at least two transistors of the plurality of transistors comprising the recessed channels and to an additional one of the plurality of transistors. The stacked capacitor, the at least two transistors and the additional one of the plurality of transistors form a memory cell of a plurality of memory cells of a memory device.

Claims

1. A method for manufacturing a semiconductor device, comprising:

forming a plurality of transistors on a semiconductor substrate, wherein forming the plurality of transistors comprises recessing channels of at least two transistors of the plurality of transistors;

forming a stacked capacitor on the semiconductor substrate;

wherein forming the stacked capacitor on the semiconductor substrate comprises;

forming a plurality of sacrificial layers on the semiconductor substrate;

forming an opening through the plurality of sacrificial layers; and

depositing a bottom capacitor electrode on bottom and lateral sides of the opening;

wherein forming the plurality of sacrificial layers comprises;

forming a second sacrificial layer on a first sacrificial layer; and

forming a third sacrificial layer on the second sacrificial layer;

wherein the first and third sacrificial layers are formed of a material which can be selectively etched with respect to the second sacrificial layer;

wherein forming the stacked capacitor on the semiconductor substrate further comprises;

selectively removing the third sacrificial layer with respect to the bottom capacitor electrode and the second sacrificial layer;

forming a dielectric spacer layer on side portions of the bottom capacitor electrode, and on portions of the second sacrificial layer;

removing exposed portions of the second sacrificial layer; and

selectively removing the dielectric spacer layer from the side portions of the bottom capacitor electrode, and from the portions of the second sacrificial layer remaining after the removal of the exposed portions of the second sacrificial layer; and

electrically connecting the stacked capacitor in parallel to the at least two transistors of the plurality of transistors comprising the recessed channels and to an additional one of the plurality of transistors;

wherein the stacked capacitor, the at least two transistors and the additional one of the plurality of transistors form a memory cell of a plurality of memory cells of a memory device.

2. The method according to claim 1, wherein the at least two transistors of the plurality of transistors respectively provide current sources for charging and discharging the memory cell.

3. The method according to claim 2, wherein the additional one of the plurality of transistors comprises a read out transistor.

4. The method according to claim 3, wherein the additional one of the plurality of transistors is without a recessed channel.

5. The method according to claim 3, wherein the additional one of the plurality of transistors comprises a shorter gate length than the gate lengths of the at least two transistors of the plurality of transistors.

6. The method according to claim 1, wherein the at least two transistors and the additional one of the plurality of transistors comprise at least one p-type field effect transistor (PFET) and at least one n-type field effect transistor (NFET).

7. The method according to claim 1, further comprising forming the plurality of memory cells in a crossbar array.

8. The method according to claim 1, wherein the recessing of the channels of the at least two transistors of the plurality of transistors comprises removing a portion of a channel region between source/drain regions for each of the at least two transistors.

9. The method according to claim 8, further comprising replacing the removed portion of the channel region with a gate structure in each of the at least two transistors.

10. The method according to claim 1, wherein forming the stacked capacitor on the semiconductor substrate further comprises selectively removing the first sacrificial layer with respect to the remaining portions of the second sacrificial layer.

11. The method according to claim 10, wherein forming the stacked capacitor on the semiconductor substrate further comprises conformally depositing a top capacitor electrode and a capacitor dielectric layer on the bottom capacitor electrode and the remaining portions of the second sacrificial layer.