Three-dimensional memory device and methods of making the same using replacement drain select gate electrodes

• US 10,629,611 B2
• Filed: 06/29/2018
• Issued: 04/21/2020
• Est. Priority Date: 04/24/2018
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Cui, Zhixin, Sakakibara, Kiyohiko, Mushiga, Mitsuteru, Otoi, Hisakazu, Sugiura, Kenji
• Primary Examiner(s): Luu, Chuong A
• Application Number:
  US16/024,048
• Publication Number:
  US 20190326313A1
• Time in Patent Office: 662 Days
• Field of Search: 257314
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/41 of a memory region comprising a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/50 characterised by the boundary region between the core region and the peripheral circuit region
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a patterned template structure around memory openings in a drain-select-level above the alternating stack, forming drain-select-level isolation structures in trenches in the patterned template structure, forming memory stack structures in the memory openings extending through the alternating stack, where each of the memory stack structures includes a memory film and a vertical semiconductor channel, replacing the sacrificial material layers with word lines, and separately replacing the patterned template structure with a drain select gate electrode.

Claims

1. A three-dimensional memory device, comprising:

an alternating stack of insulating layers and electrically conductive layers located over a substrate;

drain-select-level electrically conductive strips located over the alternating stack;

a drain-select-level isolation structure located between a neighboring pair of the drain-select-level electrically conductive strips;

memory stack structures extending through the alternating stack and the drain-select-level electrically conductive strips and comprising a respective vertical semiconductor channel vertically extending through the alternating stack and a respective one of the drain-select-level electrically conductive strips; and

dielectric cores laterally surrounded by a respective one of the vertical semiconductor channels, wherein each of the dielectric cores includes a respective core cavity devoid of any solid state material therein,

wherein each vertical semiconductor channel comprises;

a respective first vertically-extending portion extending through levels of the electrically conductive layers and having a first maximum lateral channel dimension; and

a respective second vertically-extending portion located at a level of the drain-select-level conductive strips and having a second maximum lateral channel dimension that is less than the first maximum lateral channel dimension.

2. The three-dimensional memory device of claim 1, wherein:

each first vertically-extending portion of the vertical semiconductor channels has a first convex outer sidewall that extends from a bottommost layer of the alternating stack and at least to a topmost one of the electrically conductive layers; and

each second-vertically extending portion of the vertical semiconductor channels has a second convex outer sidewall that extends through a respective one of the drain-select-level electrically conductive strips.

3. The three-dimensional memory device of claim 2, wherein:

the three-dimensional memory device comprises a three-dimensional NAND memory device;

the electrically conductive layers comprise word lines of the three-dimensional NAND memory device; and

the drain-select-level electrically conductive strips comprise drain select gate electrodes of the three-dimensional NAND memory device.

4. The three-dimensional memory device of claim 3, wherein:

the second convex outer sidewall is laterally offset inward from the first convex outer sidewall by a uniform lateral offset distance in each of the vertical semiconductor channels;

the first convex outer sidewall comprises a first cylindrical sidewall; and

the second convex outer sidewall comprises a second cylindrical sidewall having a same rotational symmetry axis as the first cylindrical sidewall.

5. The three-dimensional memory device of claim 4, wherein each of the vertical semiconductor channels comprises an annular horizontal connection portion adjoining a top end of the respective first vertically-extending portion and a bottom end of the respective second vertically-extending portion, and contacting an annular horizontal bottom surface of a tunneling dielectric that continuously extends at least from a bottommost one of the electrically conductive layers and at least to a topmost one of the drain-select-level electrically conductive strips.

6. The three-dimensional memory device of claim 1, wherein

the core cavity is located entirely underneath a horizontal plane including bottom surfaces of the drain-select-level electrically conductive strips;

the core cavity has a greater lateral extent than an overlying one of the second vertically-extending portions of the vertical semiconductor channels;

an interior of the first vertically-extending portion of each vertical semiconductor channel is filled by a respective one of the dielectric cores and a respective core cavity; and

an interior of the second vertically-extending portion of each vertical semiconductor channel is completely filled by a respective one of the dielectric cores.

7. The three-dimensional memory device of claim 1, wherein each memory stack structure comprises a memory film, which comprises:

a first vertically-extending portion that extends vertically through the alternating stack;

a horizontally-extending portion that extends horizontally above a topmost one of the electrically conductive layers and below the drain-select-level electrically conductive strips; and

a second vertically-extending portion that extends vertically through a respective one of the drain-select-level electrically conductive strips.

8. The three-dimensional memory device of claim 7, wherein:

each memory film comprises a stack of a blocking dielectric, a charge storage layer, and a tunneling dielectric;

an entirety of the charge storage layer is located below a bottom surface of one of the drain-select-level electrically conductive strips; and

the blocking dielectric directly contacts the tunneling dielectric around a respective one of the second vertically-extending portions of the vertical semiconductor channels.

9. The three-dimensional memory device of claim 7, wherein:

each memory film comprises a stack of a blocking dielectric, a charge storage layer, and a tunneling dielectric; and

each of the blocking dielectric, the charge storage layer, and the tunneling dielectric laterally surrounds a respective one of the second vertically-extending portions of the vertical semiconductor channels and vertically extends up to a horizontal plane including top surfaces of drain regions that overlie the memory stack structures.

10. The three-dimensional memory device of claim 1, wherein:

each of the memory stack structures contact, and are completely laterally surrounded by, a cylindrical sidewall of a respective one of the drain-select-level electrically conductive strips; and

a contact level dielectric layer overlies the drain-select-level electrically conductive strips, the drain-select-level isolation structure and the memory stack structures, wherein the contact level dielectric layer contacts the drain-select-level isolation structure.

11. The three-dimensional memory device of claim 1, wherein each of the drain-select-level electrically conductive strips has a respective laterally alternating sequence of planar vertical sidewall segments and convex vertical sidewall segments.

12. The three-dimensional memory device of claim 1, wherein each of the dielectric cores is laterally spaced from the alternating stack and from the drain-select-level electrically conductive strips by a respective one of the vertical semiconductor channels.

13. A three-dimensional memory device, comprising:

an alternating stack of insulating layers and electrically conductive layers located over a substrate;

drain-select-level electrically conductive strips located over the alternating stack;

a drain-select-level isolation structure located between a neighboring pair of the drain-select-level electrically conductive strips; and

memory stack structures extending through the alternating stack and the drain-select-level electrically conductive strips and comprising a respective memory film and a respective vertical semiconductor channel that vertically extend through the alternating stack and a respective one of the drain-select-level electrically conductive strips; and

wherein each vertical semiconductor channel comprises;

a respective first vertically-extending portion extending through levels of the electrically conductive layers and having a first maximum lateral channel dimension;

a respective second vertically-extending portion located at a level of the drain-select-level conductive strips and having a second maximum lateral channel dimension that is less than the first maximum lateral channel dimension; and

a respective annular horizontal connection portion adjoining a top end of the respective first vertically-extending portion and a bottom end of the respective second vertically-extending portion.

14. The three-dimensional memory device of claim 13, wherein the respective annular horizontal connection portion includes an upper annular horizontal surface having an inner periphery that coincides with a bottom periphery of an inner sidewalls of the respective second vertically-extending portion and having an outer periphery that coincides with a top periphery of an outer sidewall of the respective first vertically extending portion.

15. The three-dimensional memory device of claim 14, wherein:

the respective annular horizontal connection portion includes a lower horizontal surface having a periphery that coincides with a top periphery of an inner sidewall of the respective first vertically extending portion; and

the lower horizontal surface of the respective annular horizontal connection portion does not include any opening therein.

16. The three-dimensional memory device of claim 15, wherein a lateral thickness of the respective first vertically-extending portion of each vertical semiconductor channel is the same as a vertical thickness of the respective annular horizontal connection portion of each vertical semiconductor channel.

17. A three-dimensional memory device, comprising:

an alternating stack of insulating layers and electrically conductive layers located over a substrate;

drain-select-level electrically conductive strips located over the alternating stack;

a drain-select-level isolation structure located between a neighboring pair of the drain-select-level electrically conductive strips; and

memory stack structures extending through the alternating stack and the drain-select-level electrically conductive strips and comprising a respective memory film and a respective vertical semiconductor channel that vertically extend through the alternating stack and a respective one of the drain-select-level electrically conductive strips,

wherein each memory film comprises a tunneling dielectric including a first vertically-extending portion that vertically extends through the alternating stack, a second vertically-extending portion that vertically extends through the drain-select-level electrically conductive strips, and a horizontal annular portion that connects an upper periphery of the first vertically-extending portion of the tunneling dielectric and a lower periphery of the second vertically-extending portion of the tunneling dielectric; and

wherein each vertical semiconductor channel comprises;

a respective first vertically-extending portion extending through levels of the electrically conductive layers and having a first maximum lateral channel dimension; and

a respective second vertically-extending portion located at a level of the drain-select-level conductive strips and having a second maximum lateral channel dimension that is less than the first maximum lateral channel dimension.

18. The three-dimensional memory device of claim 17, wherein each memory film comprises:

a charge storage layer that extends through the alternating stack and contacting an outer sidewall of the first vertically-extending portion of the tunneling dielectric; and

a blocking dielectric that extends through each layer of the alternating stack and each of the drain-select-level electrically conductive strips as a single continuous material layer and contacting an outer sidewall of the charge storage layer at each level of the alternating stack and contacting the outer sidewall of the charge storage layer at each level of the drain-select-level electrically conductive strips.

19. The three-dimensional memory device of claim 17, wherein each memory film comprises:

a charge storage layer that extends through the alternating stack and contacting an outer sidewall of the first vertically-extending portion of the tunneling dielectric; and

a blocking dielectric that extends through each layer of the alternating stack and each of the drain-select-level electrically conductive strips as a single continuous material layer and contacting an outer sidewall of the charge storage layer at each level of the alternating stack and contacting an outer sidewall of the tunneling dielectric at each level of the drain-select-level electrically conductive strips.