Semiconductor memory device and method for forming the same

• US 10,629,614 B2
• Filed: 12/14/2018
• Issued: 04/21/2020
• Est. Priority Date: 07/12/2018
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: Oh, Sung-Lae
• Primary Examiner(s): Tran, Michael T
• Application Number:
  US16/220,892
• Publication Number:
  US 20200020714A1
• Time in Patent Office: 494 Days
• Field of Search: 36518501, 36518524
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/50 characterised by the boundary region between the core region and the peripheral circuit region
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions
• CPC Class Codes: H10N 70/841 Electrodes
• CPC Class Codes: H10N 70/883 Oxides or nitrides

Abstract

A semiconductor memory device includes a substrate defined with a first cell region, a slimming region extending from the first cell region in a first direction and a second cell region extending from the slimming region in the first direction; first and second electrode structures each including electrodes which are stacked on the substrate, and disposed to be separated from each other in a second direction crossing with the first direction, with a slit interposed therebetween; and a plurality of step-shaped holes disposed in the slimming region along the first direction, and respectively formed in the first and second electrode structures. Each of the step-shaped holes includes first step structures which face each other in the first direction, are symmetrical to each other and are separated by the slit and second step structures which face each other in the second direction and are symmetrical to each other.

Claims

1. A semiconductor memory device comprising:

a substrate defined with a first cell region, a slimming region extending from the first cell region in a first direction and a second cell region extending from the slimming region in the first direction;

first and second electrode structures each including a plurality of electrodes which are stacked on the substrate, and disposed to be separated from each other in a second direction crossing with the first direction, with a slit interposed therebetween; and

a plurality of step-shaped holes disposed in the slimming region along the first direction, and respectively formed in the first and second electrode structures,

wherein each of the step-shaped holes includes first step structures which face each other in the first direction, are symmetrical to each other and are separated by the slit and second step structures which face each other in the second direction and are symmetrical to each other.

2. The semiconductor memory device according to claim 1, wherein each of the step-shaped holes has a width measured in the second direction that is less than the total width of the first electrode structure, the second electrode structure and the slit measured in the second direction.

3. The semiconductor memory device according to claim 1, wherein each of the first step structures and the second step structures includes a plurality of steps which have the same height.

4. The semiconductor memory device according to claim 3, wherein a height of each of the steps is the same as a vertical pitch of the electrodes.

5. The semiconductor memory device according to claim 3, wherein the first step structures and the second step structures include the same number of steps.

6. The semiconductor memory device according to claim 1, further comprising:

step-shaped trenches vertically penetrating portions of the electrodes in the slimming region and each including third step structures which face each other in the first direction and are symmetrical to each other,

wherein, when viewed from the top, the step-shaped trenches intersect with the first and second step-shaped holes and traverse the first and second electrode structures in the second direction.

7. The semiconductor memory device according to claim 6, wherein the electrodes comprise:

a plurality of first electrodes not divided by the step-shaped trenches; and

N (N is a natural number of 2 or more) number of second electrodes stacked on the first electrodes and divided by the step-shaped trenches.

8. The semiconductor memory device according to claim 7, wherein the number of the first electrodes is greater than N.

9. The semiconductor memory device according to claim 7, wherein the first step structures and the second step structures include a plurality of steps which have the same height.

10. The semiconductor memory device according to claim 9, wherein a height of each of the steps has a size corresponding to K times the vertical pitch of the electrodes, and K is a natural number between 2 and N+1.

11. The semiconductor memory device according to claim 7, wherein each of the third step structures includes a plurality of steps which have the same height.

12. The semiconductor memory device according to claim 11, wherein a height of each of the steps is the same as the vertical pitch of the electrodes.

13. A method for forming a semiconductor memory device, comprising:

forming a stack by alternately stacking first and second material layers on a substrate including a first cell region, a slimming region extending from the first cell region in a first direction and a second cell region extending from the slimming region in the first direction;

forming a hole type mask pattern having first opening holes which are disposed in a line along the first direction, on the stack;

forming first step-shaped holes each including a pair of first step structures which face each other in the first direction and are symmetrical to each other and a pair of second step structures which face each other in a second direction crossing with the first direction and are symmetrical to each other, by etching the stack through a pad etching process using the hole type mask pattern as an etch barrier;

forming a second step-shaped hole by etching the stack such that at least one of the first step-shaped holes is recessed; and

dividing the stack by forming a slit which traverses the first and second step-shaped holes in the first direction, in the stack.

14. The method according to claim 13, further comprising:

performing a trimming process of increasing widths of the first opening holes in the first direction and the second direction, after performing the pad etching process,

wherein the pad etching process and the trimming process are alternately and repeatedly performed.

15. The method according to claim 14, wherein the pad etching process etches the first and second material layers at a depth corresponding to a vertical pitch of the first material layers.

16. The method according to claim 13, further comprising, after the forming of the stack and before the forming of the hole type mask pattern:

forming a line type mask pattern having line type openings which respectively traverse portions to be formed with the first and second step-shaped holes, on the stack; and

forming step-shaped trenches each including a pair of third step structures which face each other in the first direction and are symmetrical to each other, by etching the stack through a unit etching process using the line type mask pattern as an etch barrier.

17. The method according to claim 16, further comprising:

performing a trimming process of increasing an opening area of the line type mask pattern, after performing the unit etching process,

wherein the unit etching process and the trimming process are alternately and repeatedly performed.

18. The method according to claim 17, wherein the unit etching process etches the first and second material layers at a depth corresponding to the vertical pitch of the first material layers.

19. The method according to claim 18, wherein, in the case where the number of unit etching processes is N (N is a natural number), an etching depth of the pad etching process is K (K is a natural number between 2 and N+1) times the vertical pitch of the first material layers.

20. A semiconductor memory device, comprising a substrate;

a stack of alternating first and second material layers on the substrate including a first cell region, a slimming region extending from the first cell region in a first direction and a second cell region extending from the slimming region in the first direction;

first and second step-shaped holes penetrating the stack at least partially in a third direction, each of the first and second step-shaped holes including a pair of first step structures which face each other in the first direction and are symmetrical to each other and a pair of second step structures which face each other in a second direction crossing with the first direction and are symmetrical to each other;

a slit which divides the stack and traverses the first and second step-shaped holes in the first direction, and

first and second step-shaped trenches each traversing the entire stack in the second direction and intersecting with the first and second step-shaped holes, respectively.