Array substrate and manufacturing method thereof, display device

• US 10,629,633 B2
• Filed: 06/28/2019
• Issued: 04/21/2020
• Est. Priority Date: 07/10/2015
• Status: Active Grant

• Current Assignee: Beijing BOE Optoelectronics Technology Co Ltd. (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Original Assignee: BOE Technology Group Co., Ltd.
• Inventors: Zhang, Hepan, Ai, Qingnan, Li, Yue
• Primary Examiner(s): Warren, Matthew E
• Application Number:
  US16/456,352
• Publication Number:
  US 20190326328A1
• Time in Patent Office: 298 Days
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1251 comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H01L 27/1262 with a particular formation, treatment or coating of the substrate
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement

Abstract

A manufacturing method of an array substrate is disclosed. The manufacturing method includes a step of forming a pattern including a pixel electrode; and the manufacturing method further includes a step of forming a pattern including an active layer after the step of forming the pattern including the pixel electrode. Accordingly, an array substrate and a display device are also disclosed. In the manufacturing process of the array substrate, conductive material remained on the active layer is less, thereby producing less leak current, which in turn improves quality of the array substrate and display performance of the display device.

Claims

1. An array substrate, comprising:

a substrate;

a thin film transistor on the substrate and comprising an active layer; and

a pixel electrode on a side of the active layer closer to the substrate, and insulated and spaced apart from the active layer; and

a buffering insulation layer on a side of the pixel electrode away from the substrate and on the side of the active layer closer to the substrate,

wherein the pixel electrode is coupled to a drain of the thin film transistor,

wherein the thin film transistor further comprises a gate on the substrate,

the array substrate further comprises a gate insulation layer on a side of the gate away from the substrate and on a side of the pixel electrode closer to the substrate,

wherein the pixel electrode is in direct contact with the buffering insulation layer, and

wherein the pixel electrode is on a side of the gate insulation layer away from the substrate and in direct contact with the gate insulation layer, and the gate is on a side of the gate insulation layer closer to the substrate than the gate insulation layer and in direct contact with the gate insulation layer.

2. The array substrate of claim 1, wherein a via is provided in the buffering insulation layer, and the drain of the thin film transistor is coupled to the pixel electrode through the via.

3. The array substrate of claim 1, wherein a source ohmic contact layer is provided between a source and the active layer of the thin film transistor, and a drain ohmic contact layer is provided between the drain and the active layer of the thin film transistor.

4. The array substrate of claim 1, further comprising:

a passivation layer on a side of the active layer away from the substrate; and

a common electrode on a side of the passivation layer away from the substrate and comprising a plurality of common electrode strips,

wherein an orthographic projection of the passivation layer on the substrate covers orthographic projections of a source and the drain of the thin film transistor and the buffering insulation layer.

5. The array substrate of claim 4, wherein at least one of a material of the buffering insulation layer and a material of the passivation layer comprises silicon nitride.

6. The array substrate of claim 4, wherein the passivation layer is in direct contact with the source, in direct contact with the drain and in direct contact with the buffering insulation layer.

7. A display device, comprising an array substrate, wherein the array substrate is the array substrate of claim 1.

8. The display device of claim 7, wherein a via is provided in the buffering insulation layer, and the drain of the thin film transistor is coupled to the pixel electrode through the via.

9. The display device of claim 7, wherein a source ohmic contact layer is provided between a source and the active layer of the thin film transistor, and a drain ohmic contact layer is provided between the drain and the active layer of the thin film transistor.

10. The display device of claim 7, wherein the array substrate further comprises:

a passivation layer on a side of the active layer away from the substrate; and

a common electrode on a side of the passivation layer away from the substrate and comprising a plurality of common electrode strips,

wherein an orthographic projection of the passivation layer on the substrate covers orthographic projections of a source and the drain of the thin film transistor and the buffering insulation layer.

11. The display device of claim 10, wherein at least one of a material of the buffering insulation layer and a material of the passivation layer comprises silicon nitride.

12. The display device of claim 10, wherein the passivation layer is in direct contact with the source, in direct contact with the drain and in direct contact with the buffering insulation layer.