Semiconductor device with cell trench structures and recessed contacts and method of manufacturing a semiconductor device

• US 10,629,676 B2
• Filed: 08/23/2018
• Issued: 04/21/2020
• Est. Priority Date: 08/09/2013
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Laven, Johannes Georg, Cotorogea, Maria, Schulze, Hans-Joachim, Itani, Haybat, Griebl, Erich, Haghofer, Andreas
• Primary Examiner(s): Ward, Eric A.
• Assistant Examiner(s): Ashbahian, Eric K
• Application Number:
  US16/110,508
• Publication Number:
  US 20180366541A1
• Time in Patent Office: 607 Days
• CPC Class Codes: H01L 21/22 Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
• CPC Class Codes: H01L 21/2236 from or into a plasma phase
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 29/06 characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0865 Disposition
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

First and second cell trench structures extend from a first surface into a semiconductor substrate. The first cell trench structure includes a first buried electrode and a first insulator layer between the first buried electrode and a semiconductor mesa separating the first and second cell trench structures. A capping layer covers the first surface. The capping layer is patterned to form an opening having a minimum width larger than a thickness of the first insulator layer. The opening exposes a first vertical section of the first insulator layer at the first surface. An exposed portion of the first insulator layer is removed to form a recess between the semiconductor mesa and the first buried electrode. A contact structure is in the opening and the recess. The contact structure electrically connects both a buried zone in the semiconductor mesa and the first buried electrode and allows for narrower semiconductor mesa width.

Claims

1. A semiconductor device, comprising:

a plurality of source zones of a first conductivity type formed in a semiconductor substrate as stripes which extend lengthwise in parallel in a first direction;

a plurality of body zones of a second conductivity type opposite the first conductivity type formed in the semiconductor substrate below the plurality of source zones;

a plurality of heavily doped contact zones formed in the body zones;

a plurality of first cell trench structures formed in the semiconductor substrate and extending lengthwise in parallel in a second direction transverse to the first direction so as to transect the stripes of source zones and the body zones, each first cell trench structure comprising a first buried electrode and a first insulator layer between the first buried electrode and the semiconductor substrate;

a plurality of second cell trench structures formed in the semiconductor substrate and extending lengthwise in parallel in the second direction so as to transect the stripes of source zones and the body zones, two or more first cell trench structures of the plurality of first cell trench structures being interposed between neighboring ones of the second cell trench structures, each second cell trench structure comprising a second buried electrode and a second insulator layer between the second buried electrode and the semiconductor substrate;

a recess formed in the first insulator layer along a sidewall of one or more of the first cell trench structures and vertically extending to the corresponding heavily doped contact zone; and

an electrically conductive material disposed in each recess formed in the first insulator layer and contacting the corresponding first buried electrode, the corresponding source zone and the corresponding heavily doped contact zone at the sidewall.

2. The semiconductor device of claim 1, wherein the sidewall of the one or more first cell trench structures with the recess is tilted by less than 90 degrees with respect to a first main surface of the semiconductor substrate into which the plurality of first cell trench structures and the plurality of second cell trench structures extend.

3. The semiconductor device of claim 1, wherein the first insulator layer has a uniform width.

4. The semiconductor device of claim 1, wherein the width of each recess increases with increasing proximity to a first main surface of the semiconductor substrate into which the plurality of first cell trench structures and the plurality of second cell trench structures extend.

5. The semiconductor device of claim 1, wherein the width of the first buried electrode in each first cell trench structure with a recessed first insulator layer decreases with increasing proximity to a first main surface of the semiconductor substrate into which the plurality of first cell trench structures and the plurality of second cell trench structures extend.

6. The semiconductor device of claim 5, wherein the width of the first buried electrode in each first cell trench structure with a recessed first insulator layer is generally uniform below the recess.

7. The semiconductor device of claim 1, further comprising a capping layer formed on a first main surface of the semiconductor substrate into which the plurality of first cell trench structures and the plurality of second cell trench structures extend, wherein the electrically conductive material disposed in each recess formed in the first insulator layer extends through openings in the capping layer to form part of an overlying contact structure.

8. The semiconductor device of claim 7, wherein the first buried electrode of one or more of the first cell trench structures is electrically contacted by the contact structure through an additional opening in the capping layer which is aligned with a top side of the first buried electrode.

9. The semiconductor device of claim 1, wherein the first buried electrodes are electrically coupled to a source potential, and wherein the second buried electrodes are electrically coupled to a gate potential.

10. The semiconductor device of claim 1, wherein the semiconductor device is an IGBT.

11. The semiconductor device of claim 1, wherein between neighboring ones of the stripes of source zones stripes, the body zones extend to a first main surface of the semiconductor substrate into which the plurality of first cell trench structures and the plurality of second cell trench structures extend.

12. The semiconductor device of claim 1, wherein interfaces between the source zones and the body zones run approximately parallel to a first surface of the semiconductor substrate into which the plurality of first cell trench structures and the plurality of second cell trench structures at a first distance, wherein a second distance between the first surface and an edge of the electrically conductive material at a bottom of each recess formed in the first insulator layer is greater than the first distance, wherein interfaces between the body zones and a drift layer of the first conductivity type run approximately parallel to the first surface at a third distance, and wherein the second distance is smaller than the third distance.

13. The semiconductor device of claim 1, wherein between first cell trench structures of the plurality of first cell trench structures for which the first buried electrode is contacted by the electrically conductive material through the recess formed in the corresponding first insulator layer, the buried electrode of at least one first cell trench structure of the plurality of first cell trench structures is contacted by the electrically conductive material only at a first main surface of the semiconductor substrate.

14. A method of manufacturing a semiconductor device, the method comprising:

forming a plurality of source zones of a first conductivity type in a semiconductor substrate as stripes which extend lengthwise in parallel in a first direction;

forming a plurality of body zones of a second conductivity type opposite the first conductivity type in the semiconductor substrate below the plurality of source zones;

forming a plurality of heavily doped contact zones in the body zones;

forming a plurality of first cell trench structures in the semiconductor substrate and extending lengthwise in parallel in a second direction transverse to the first direction so as to transect the stripes of source zones and the body zones, each first cell trench structure comprising a first buried electrode and a first insulator layer between the first buried electrode and the semiconductor substrate;

forming a plurality of second cell trench structures in the semiconductor substrate and extending lengthwise in parallel in the second direction so as to transect the stripes of source zones and the body zones, two or more first cell trench structures of the plurality of first cell trench structures being interposed between neighboring ones of the second cell trench structures, each second cell trench structure comprising a second buried electrode and a second insulator layer between the second buried electrode and the semiconductor substrate;

forming a recess in the first insulator layer along a sidewall of one or more of the first cell trench structures and vertically extending to the corresponding heavily doped contact zone; and

disposing an electrically conductive material in each recess formed in the first insulator layer so as to contact the corresponding first buried electrode, the corresponding source zone and the corresponding heavily doped contact zone at the sidewall.

15. The method of claim 14, wherein forming the recess in the first insulator layer along a sidewall of the one or more first cell trench structures comprises tilting the sidewall of the one or more first cell trench structures by less than 90 degrees with respect to a first main surface of the semiconductor substrate into which the plurality of first cell trench structures and the plurality of second cell trench structures extend.

16. The method of claim 15, wherein tilting the sidewall of the one or more first cell trench structures by less than 90 degrees with respect to the first main surface of the semiconductor substrate comprises removing a material of the buried first electrode at an etch selectivity with respect to a material of the semiconductor substrate of at least 5:

1.

17. The method of claim 14, wherein forming the recess in the first insulator layer along a sidewall of the one or more first cell trench structures comprises decreasing the width of each recess with decreasing proximity to a first main surface of the semiconductor substrate into which the plurality of first cell trench structures and the plurality of second cell trench structures extend.

18. The method of claim 17, wherein the width of the first buried electrode in each first cell trench structure with a recessed first insulator layer is generally uniform below the recess.

19. The method of claim 14, further comprising:

forming a capping layer on a first main surface of the semiconductor substrate into which the plurality of first cell trench structures and the plurality of second cell trench structures extend, wherein the electrically conductive material disposed in each recess formed in the first insulator layer extends through openings in the capping layer to form part of an overlying contact structure.

20. The method of claim 19, further comprising:

electrically contacting the first buried electrode of one or more of the first cell trench structures by the contact structure through an additional opening in the capping layer which is aligned with a top side of the first buried electrode.

21. The method of claim 14, further comprising:

electrically coupling the first buried electrodes to a source potential; and

electrically coupling the second buried electrodes to a gate potential.