Manufacturable thin film gallium and nitrogen containing devices

• US 10,629,689 B1
• Filed: 06/11/2018
• Issued: 04/21/2020
• Est. Priority Date: 12/23/2014
• Status: Active Grant

• Current Assignee: Kyocera SLD Laser Incorporated (Kyocera Corporation)
• Original Assignee: Soraa Laser Diode, Inc. (Kyocera Corporation)
• Inventors: Raring, James W., McLaurin, Melvin, Sztein, Alexander, Hsu, Po Shan
• Primary Examiner(s): Geyer, Scott B
• Application Number:
  US16/005,255
• Time in Patent Office: 680 Days
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/311 Etching the insulating layers by chemical or physical means H01L21/31058 takes precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/8252 the substrate being a semiconductor, using III-V technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 21/8258 the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
• CPC Class Codes: H01L 2221/68354 used to support diced chips prior to mounting
• CPC Class Codes: H01L 2221/68368 used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
• CPC Class Codes: H01L 2221/68377 with parts of the auxiliary support remaining in the finished device
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/83005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/83191 wherein the layer connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83801 Soldering or alloying
• CPC Class Codes: H01L 2224/8385 using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 2224/8389 using an inorganic non metallic glass type adhesive, e.g. solder glass
• CPC Class Codes: H01L 2224/83895 between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
• CPC Class Codes: H01L 2224/83896 between electrically insulating surfaces, e.g. oxide or nitride layers
• CPC Class Codes: H01L 2224/95 at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
• CPC Class Codes: H01L 2224/95001 involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
• CPC Class Codes: H01L 24/00 Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/95 : at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
• CPC Class Codes: H01L 27/0605 : integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 27/0629 : in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/0676 : comprising combinations of diodes, or capacitors or resistors
• CPC Class Codes: H01L 27/085 : including field-effect components only
• CPC Class Codes: H01L 27/088 : the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/1255 : integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/1259 : Multistep manufacturing methods
• CPC Class Codes: H01L 27/15 : including semiconductor components having potential barriers, specially adapted for light emission
• CPC Class Codes: H01L 29/1066 : Gate region of field-effect devices with PN junction gate
• CPC Class Codes: H01L 29/2003 : Nitride compounds
• CPC Class Codes: H01L 29/205 : in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/4236 : within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/432 : Heterojunction gate for field effect devices
• CPC Class Codes: H01L 29/66136 : PN junction diodes
• CPC Class Codes: H01L 29/66143 : Schottky diodes
• CPC Class Codes: H01L 29/66318 : Heterojunction transistors
• CPC Class Codes: H01L 29/66462 : with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/66916 : with a PN heterojunction gate
• CPC Class Codes: H01L 29/7786 : with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
• CPC Class Codes: H01L 29/8613 : Mesa PN junction diodes
• CPC Class Codes: H01L 29/872 : Schottky diodes
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/1203 : Rectifying Diode
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13062 : Junction field-effect transistor [JFET]
• CPC Class Codes: H01L 2924/13064 : High Electron Mobility Transistor [HEMT, HFET [heterostructure FET], MODFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 33/0025 : comprising only AIIIBV compounds
• CPC Class Codes: H01L 33/0066 : with a substrate not being a III-V compound
• CPC Class Codes: H01L 33/007 : comprising nitride compounds
• CPC Class Codes: H01L 33/0075 : comprising nitride compounds
• CPC Class Codes: H01L 33/0093 : Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/06 : within the light emitting region, e.g. quantum confinement structure or tunnel barrier
• CPC Class Codes: H01L 33/32 : containing nitrogen
• CPC Class Codes: H01S 5/0203 : Etching
• CPC Class Codes: H01S 5/0217 : Removal of the substrate
• CPC Class Codes: H01S 5/227 : Buried mesa structure ; Striped active layer
• CPC Class Codes: H01S 5/34333 : with a well layer based on Ga(In)N or Ga(In)P, e.g. blue laser

Abstract

A method for manufacturing a display panel comprising light emitting device including micro LEDs includes providing multiple donor wafers having a surface region and forming an epitaxial material overlying the surface region. The epitaxial material includes an n-type region, an active region comprising at least one light emitting layer overlying the n-type region, and a p-type region overlying the active layer region. The multiple donor wafers are configured to emit different color emissions. The epitaxial material on the multiple donor wafers is patterned to form a plurality of dice, characterized by a first pitch between a pair of dice less than a design width. At least some of the dice are selectively transferred from the multiple donor wafers to a common carrier wafer such that the carrier wafer is configured with different color emitting LEDs. The different color LEDs could comprise red-green-blue LEDs to form a RGB display panel.

Claims

1. A partially completed semiconductor device for processing, comprising:

a plurality of dies arranged in an array and overlying a surface region of a gallium and nitrogen containing substrate, each of the plurality of dies comprising an epitaxial material, the epitaxial material comprising a release material overlying the gallium and nitrogen containing substrate and at least an intrinsic-type or unintentionally doped gallium and nitrogen containing region overlying the release material or at least an n-type gallium and nitrogen containing region overlying the release material or at least a p-type gallium and nitrogen containing region overlying the release material or at least a combination of one or more of the n-type gallium and nitrogen containing region, the p-type gallium and nitrogen containing region, and the intrinsic-type or unintentionally doped gallium and nitrogen containing region overlying the release material, wherein adjacent ones of the plurality of dies in the array are separated by a first pitch;

interface regions overlying the epitaxial material of the plurality of dies, each of the interface regions comprising a metal, a semiconductor, dielectric, oxide, glass, or a polymer, wherein at least a portion of the interface regions are bonded to a carrier wafer to form a bonded structure;

wherein the plurality of dies provided on the gallium and nitrogen containing substrate are releasable to transfer at least the portion of the plurality of dies to the carrier wafer, wherein adjacent pairs of the transferred dies are configured with a second pitch on the carrier wafer, the second pitch being equal to or greater than the first pitch.

2. The partially completed semiconductor device of claim 1 wherein the carrier wafer has a larger diameter and/or a larger total surface area than the gallium and nitrogen containing substrate.

3. The partially completed semiconductor device of claim 1, wherein the carrier wafer is selected from a sapphire wafer, silicon carbide wafer, aluminum nitride wafer, silicon wafer, gallium arsenide wafer, diamond wafer, gallium nitride wafer, or an indium phosphide wafer.

4. The partially completed semiconductor device of claim 1, wherein the release material is selected from GaN, InGaN, AlInGaN, or AlGaN.

5. The partially completed semiconductor device of claim 1, wherein each of the plurality of dies comprises one or more components, the one or more components being selected from at least one of an electrical contact bond pad, a light emitting region, a current spreading region, an optical cladding region, a drift region, an insulation region, an edge termination region, an emitter region, a base region, a collector region, a gate region, an isolation region, or a passivation region either alone or in any combination.

6. The partially completed semiconductor device of claim 1, wherein the epitaxial material comprises an active region configured between an n-type gallium and nitrogen containing material and a p-type gallium and nitrogen containing material;

wherein the active region comprises one or more light emitting layers configured to emit electromagnetic radiation in the ultra-violet, violet, blue, green, or red wavelength regime.

7. The partially completed semiconductor device of claim 1, wherein the epitaxial material comprises an active region configured between an n-type gallium and nitrogen containing material and a p-type gallium and nitrogen containing material;

wherein the active region comprises one or more light emitting layers configured to emit electromagnetic radiation in the violet, blue, green, or red wavelength regime; and

the epitaxial material further comprises a cladding region above and below the active region; and

the epitaxial material further comprises a ridge waveguide structure; and

a first facet region formed on a first end of the ridge waveguide region and a second facet region formed on a second end of the ridge waveguide region.

8. The partially completed semiconductor device of claim 1, wherein the epitaxial material comprises an n-type gallium and nitrogen containing material and an intrinsic or unintentionally doped drift region comprising a gallium and nitrogen containing material;

wherein the intrinsic or unintentionally doped drift region has a carrier concentration of less than about 1E17 cm<sup>−

3</sup> or less than about 5E16 cm<sup>−

3</sup> or less than about 1E16 cm<sup>−

3</sup> and a thickness of less than about 60 μ

m, less than about 30 μ

m, or less than about 10 μ

m; and

wherein the dopants in the intrinsic or unintentionally doped drift region are comprised of intentional dopants or non-intentional dopants or a combination thereof.

9. The partially completed semiconductor device of claim 8, wherein the n-type gallium and nitrogen containing material is comprised of gallium nitride and the intrinsic or unintentionally doped drift region is comprised of gallium nitride.

10. The partially completed semiconductor device of claim 8, wherein the intrinsic or unintentionally doped drift region has a carrier concentration of less than 5E15 cm⁻

3 or less than 1E15 cm<sup>−

3</sup>.

11. The partially completed semiconductor device of claim 8, wherein an edge termination region is formed to reduce the peak electric field along a contact edge;

and wherein the edge termination is formed using a mesa structure, guard rings, field plates, high resistivity region by ion implantation, or a combination thereof;

wherein the partially completed semiconductor device is a vertical structure.

12. The partially completed semiconductor device of claim 1, wherein the epitaxial material comprises an n-type gallium and nitrogen containing material, an intrinsic or unintentionally doped drift region comprising a gallium and nitrogen containing material, and a p-type gallium and nitrogen containing material;

and wherein the intrinsic or unintentionally doped drift region has a carrier concentration of less than about 1E17 cm<sup>−

3</sup> or less than about 5E16 cm<sup>−

3</sup> or less than about 1E16 cm<sup>−

3</sup> and a thickness of less than about 60 μ

m, less than about 30 μ

m, or less than about 10 μ

m; and

wherein the dopants in the intrinsic or unintentionally doped drift region are comprised of intentional dopants or non-intentional dopants or a combination thereof.

13. The partially completed semiconductor device of claim 12, wherein the n-type gallium and nitrogen containing material is comprised of gallium nitride and the intrinsic or unintentionally doped drift region is comprised of gallium nitride.

14. The partially completed semiconductor device of claim 12, wherein the intrinsic or unintentionally doped drift region has a total active carrier concentration of less than 5E15 cm⁻

3 or less than 1E15 cm<sup>−

3</sup>.

15. The partially completed semiconductor device of claim 1, wherein the epitaxial material comprises a first nitrogen containing material with a first bandgap and a second gallium and nitrogen containing material with a second bandgap;

and

wherein the first bandgap is greater than the second bandgap and wherein the first and second materials form a heterojunction interface; and

further comprising a source region, a drain region, and a gate region.

16. The partially completed semiconductor device of claim 1, wherein the epitaxial material comprises an n-type gallium and nitrogen containing material and a p-type gallium and nitrogen containing material;

and the epitaxial material further comprises a source region, a drain region, and a gate region.

17. The partially completed semiconductor device of claim 1, wherein the epitaxial material comprises an n-type gallium and nitrogen containing material and a p-type gallium and nitrogen containing material.