Method and device for shallow trench isolation in a fin type field effect transistors

• US 10,629,741 B1
• Filed: 10/30/2018
• Issued: 04/21/2020
• Est. Priority Date: 10/30/2018
• Status: Active Grant

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Sung, Min Gyu, Van Meer, Johannes
• Primary Examiner(s): Lee, Jae
• Application Number:
  US16/175,494
• Publication Number:
  US 20200135928A1
• Time in Patent Office: 539 Days
• CPC Class Codes: H01L 21/31155 by ion implantation
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7846 the means being located in the lateral device isolation region, e.g. STI
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors

Abstract

A method of forming a semiconductor device may include providing a semiconductor device structure. The semiconductor device structure may include semiconductor fins pitched at a fin pitch on a substrate. The semiconductor device structure may include an isolation oxide layer on the substrate and between the semiconductor fins and a mask. The mask may be disposed over the isolation oxide layer and the mask may define at least one opening. The method may further comprise directing hot ions into the at least one opening, to implant hot ions in a volume of isolation oxide in the isolation oxide layer. The volume may be adjacent to at least one of the semiconductor fins.

Claims

1. A method of forming a semiconductor device, comprising:

providing a semiconductor device structure, the semiconductor device structure comprising;

semiconductor fins pitched at a fin pitch on a substrate;

an isolation oxide layer on the substrate and between the semiconductor fins;

a mask, disposed over the isolation oxide layer, the mask defining a at least one opening;

forming a hard mask layer over the semiconductor fins;

removing a portion of the semiconductor fins to reveal two pairs of the semiconductor fins, a first pair of the semiconductor fins to form channels for p-channel metal oxide field effect transistors and a second pair of the semiconductor fins to form channels for n-channel metal oxide field effect transistors;

forming the isolation oxide layer on the substrate and between the semiconductor fins;

forming the mask with the at least one opening over ends of the first pair of the semiconductor fins;

directing hot ions into the at least one opening, to implant hot ions in a volume of isolation oxide in the isolation oxide layer, the volume adjacent to at least one of the semiconductor fins; and

removing the hard mask.

2. The method of claim 1, further comprising forming a second mask disposed over the isolation oxide layer, the second mask having an opening to expose an end of at least a second fin of the semiconductor fins and directing hot ions into the at least one opening, to implant hot ions in a second volume of isolation oxide in the isolation oxide layer, the second volume adjacent to the end of the at least a second fin of the semiconductor fins.

3. The method of claim 1, wherein the hard mask extends at least partially down sides of the at least one of the semiconductor fins.

4. The method of claim 1, wherein the directing the hot ions into the at least one opening comprises directing hot ions into the volume of the isolation oxide at an atomic concentration to attenuate or neutralize a tensile stress imposed on the at least one of the semiconductor fins via densification and annealing of an isolation oxide adjacent to the at least one of the semiconductor fins.

5. The method of claim 1, wherein the directing the hot ions into the at least one opening comprises directing hot ions into the volume of the isolation oxide at an atomic concentration to add a compressive stress in parallel with the at least one of the semiconductor fins.

6. The method of claim 5, wherein the mask is disposed over a second volume of isolation oxide in the isolation oxide layer, the second volume of isolation oxide adjacent to an end of at least a second one of the semiconductor fins.

7. The method of claim 6, wherein the at least one opening is disposed over the second volume of isolation oxide in the isolation oxide layer.