Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals
First Claim
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1. An integrated circuit block comprising:
- a first node;
a second node;
a series arrangement of one or more capacitors;
a series arrangement of a plurality of switches,a first compensation capacitor having a first compensation capacitor first terminal and a first compensation capacitor second terminal; and
a second compensation capacitor having a second compensation capacitor first terminal and a second compensation capacitor second terminal;
wherein;
the one or more capacitors are in series with the plurality of switches;
a combination of the one or more capacitors and the plurality of switches is coupled between the first node and the second node;
the plurality of switches are configured to withstand a voltage greater than a voltage withstood by one switch;
the plurality of switches are configured to receive a control signal to enable or disable the switches and thereby adjusting the capacitance between the two nodes,the first compensation capacitor first terminal is directly connected to a first switch terminal of a first switch of the plurality of switches, and the first compensation capacitor second terminal is directly connected to a second switch terminal of the first switch of the plurality of switches;
the second compensation capacitor first terminal is directly connected to the first switch terminal of the first switch of the plurality of switches, and the second compensation capacitor second terminal is directly connected to a switch terminal of a j-th switch of the plurality of switches;
wherein the first compensation capacitor and second compensation capacitor are not connected in parallel across the first switch nor connected in series to each other; and
j is an integer greater or equal to two and less than or equal to a number of switches of the plurality of switches.
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Abstract
Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.
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Citations
20 Claims
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1. An integrated circuit block comprising:
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a first node; a second node; a series arrangement of one or more capacitors; a series arrangement of a plurality of switches, a first compensation capacitor having a first compensation capacitor first terminal and a first compensation capacitor second terminal; and a second compensation capacitor having a second compensation capacitor first terminal and a second compensation capacitor second terminal; wherein; the one or more capacitors are in series with the plurality of switches; a combination of the one or more capacitors and the plurality of switches is coupled between the first node and the second node; the plurality of switches are configured to withstand a voltage greater than a voltage withstood by one switch; the plurality of switches are configured to receive a control signal to enable or disable the switches and thereby adjusting the capacitance between the two nodes, the first compensation capacitor first terminal is directly connected to a first switch terminal of a first switch of the plurality of switches, and the first compensation capacitor second terminal is directly connected to a second switch terminal of the first switch of the plurality of switches; the second compensation capacitor first terminal is directly connected to the first switch terminal of the first switch of the plurality of switches, and the second compensation capacitor second terminal is directly connected to a switch terminal of a j-th switch of the plurality of switches;
wherein the first compensation capacitor and second compensation capacitor are not connected in parallel across the first switch nor connected in series to each other; andj is an integer greater or equal to two and less than or equal to a number of switches of the plurality of switches. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 20)
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14. An integrated circuit block comprising:
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a first node; a second node; a series arrangement of one or more capacitors; a series arrangement of a plurality of switches comprising; i) a first set of switches, proceeding from a first switch of the first set of switches closest to the first node and farthest from the second node to an n1-th switch of the first set of switches closest to the second node and farthest from the first node; and ii) a second set of switches, proceeding from a first switch of the second set of switches closest to the second node and farthest from the first node to an n2-th switch of the second set of switches closest to the first node and farthest to the second node, n1 and n2 being integers larger than 1; a first compensation capacitor having a first compensation capacitor first terminal and a first compensation capacitor second terminal; and a second compensation capacitor having a second compensation capacitor first terminal and a second compensation capacitor second terminal;
a third compensation capacitor having a third compensation capacitor first terminal and a third compensation capacitor second terminal;
wherein;the one or more capacitors are in series with the plurality of switches; a combination of the one or more capacitors and the plurality of switches is coupled between the first node and the second node; the plurality of switches are configured to withstand a voltage greater than a voltage configured to be withstood by one switch; the plurality of switches are configured to receive a control signal to enable or disable switches of the plurality of switches and thereby adjusting capacitance between the two nodes; the first compensation capacitor first terminal is directly connected to a first switch terminal of a first switch of the first set of switches, and the first compensation capacitor second terminal is directly connected to a switch terminal consisting of one of i) a second switch terminal of the first switch of the first set of switches or ii) a first switch terminal of an i-th switch of the first set of switches, or iii) a second switch terminal of the i-th switch of the first set of switches;
the second compensation capacitor first terminal is directly connected to the first switch terminal of the first switch of the first set of switches, and the second compensation capacitor second terminal is directly connected to a switch terminal of a k-th switch of the first set of switches, wherein the first compensation capacitor and second compensation capacitor are not connected in parallel across the first switch nor connected in series to each other;the third compensation capacitor first terminal is directly connected to a first switch terminal of a first switch of the second set of switches, and the third compensation capacitor second terminal is directly connected to one of i) a second switch terminal of the first switch of the second set of switches or ii) a first switch terminal of a j-th switch of the second set of switches, or iii) a second switch terminal of the j-th switch of the second set of switches; i is an integer greater than one and less than or equal to n1; and j is an integer greater than one and less than or equal to n2. - View Dependent Claims (15, 16, 17, 18, 19)
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Specification