Logic drive with brain-like elasticity and integrality based on standard commodity FPGA IC chips using non-volatile memory cells
First Claim
1. A chip package comprising:
- an interposer comprising a silicon substrate, a plurality of metal vias passing through the silicon substrate, a first interconnection metal layer over the silicon substrate, a second interconnection metal layer over the silicon substrate and the first interconnection metal layer, and an insulating dielectric layer over the silicon substrate and between the first and second interconnection metal layers;
a first semiconductor integrated-circuit (IC) chip over the interposer, wherein the first semiconductor integrated-circuit (IC) chip couples to the interposer, wherein the first semiconductor integrated-circuit (IC) chip comprises a programmable logic circuit configured to be programmed to perform a logic operation, comprising a plurality of first non-volatile memory cells configured to store a plurality of resulting values of a look-up table (LUT) respectively, a plurality of first latch circuits coupling to the plurality of first non-volatile memory cells respectively, wherein each of the plurality of first latch circuits is configured to latch data associated with one of the plurality of resulting values of the look-up table (LUT) from a first non-volatile memory cell of the plurality of first non-volatile memory cells, a first multiplexer comprising a first set of input points for a first input data set for the logic operation and a second set of input points for a second input data set associated with the data latched in the plurality of first latch circuits, wherein the first multiplexer is configured to select, in accordance with the first input data set, an input data from the second input data set as an output data for the logic operation; and
a plurality of first metal bumps at a bottom of the interposer, wherein the plurality of first metal bumps couple to the plurality of metal vias respectively.
1 Assignment
0 Petitions
Accused Products
Abstract
A chip package comprises an interposer; an FPGA IC chip over the interposer, wherein the FPGA IC chip comprises a programmable logic block configured to perform a logic operation on its inputs, wherein the programmable logic block comprises a look-up table configured to be provided with multiple resulting values of the logic operation on multiple combinations of the inputs of the programmable logic block respectively, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output, and multiple non-volatile memory cells configured to save the resulting values respectively; multiple first metal bumps between the interposer and the FPGA IC chip; and an underfill between the interposer and the FPGA IC chip, wherein the underfill encloses the first metal bumps.
94 Citations
26 Claims
-
1. A chip package comprising:
-
an interposer comprising a silicon substrate, a plurality of metal vias passing through the silicon substrate, a first interconnection metal layer over the silicon substrate, a second interconnection metal layer over the silicon substrate and the first interconnection metal layer, and an insulating dielectric layer over the silicon substrate and between the first and second interconnection metal layers; a first semiconductor integrated-circuit (IC) chip over the interposer, wherein the first semiconductor integrated-circuit (IC) chip couples to the interposer, wherein the first semiconductor integrated-circuit (IC) chip comprises a programmable logic circuit configured to be programmed to perform a logic operation, comprising a plurality of first non-volatile memory cells configured to store a plurality of resulting values of a look-up table (LUT) respectively, a plurality of first latch circuits coupling to the plurality of first non-volatile memory cells respectively, wherein each of the plurality of first latch circuits is configured to latch data associated with one of the plurality of resulting values of the look-up table (LUT) from a first non-volatile memory cell of the plurality of first non-volatile memory cells, a first multiplexer comprising a first set of input points for a first input data set for the logic operation and a second set of input points for a second input data set associated with the data latched in the plurality of first latch circuits, wherein the first multiplexer is configured to select, in accordance with the first input data set, an input data from the second input data set as an output data for the logic operation; and a plurality of first metal bumps at a bottom of the interposer, wherein the plurality of first metal bumps couple to the plurality of metal vias respectively. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
-
Specification