Analog-to-digital converter with low inter-symbol interference and reduced common-mode voltage mismatch

• US 10,630,308 B2
• Filed: 04/15/2019
• Issued: 04/21/2020
• Est. Priority Date: 07/20/2018
• Status: Active Grant

• Current Assignee: Realtek Semiconductor Corp.
• Original Assignee: Realtek Semiconductor Corp.
• Inventors: Wu, Ying-Cheng, Huang, Shih-Hsiung
• Primary Examiner(s): Pierre, Peguy Jean
• Application Number:
  US16/383,731
• Publication Number:
  US 20200028518A1
• Time in Patent Office: 372 Days
• Field of Search: 341122, 341155
• CPC Class Codes: H03K 5/24 the characteristic being amplitude
• CPC Class Codes: H03M 1/1245 Details of sampling arrangements or methods
• CPC Class Codes: H03M 1/442 using switched capacitors
• CPC Class Codes: H03M 1/468 in which the input S/H circuit is merged with the feedback DAC array

Abstract

The present invention discloses an analog-to-digital converter (ADC) including an analog circuit, a first switch, a second switch, a first capacitor, and a second capacitor. The analog circuit has a first input terminal and a second input terminal and is configured to amplify and/or compare signals on the first input terminal and the second input terminal. One end of the first capacitor is coupled to the first input terminal, and the other end receives an input voltage via the first switch. One end of the second capacitor is coupled to the first input terminal, and the other end receives a reference voltage via the second switch.

Claims

1. An analog-to-digital converter (ADC) comprising:

an analog circuit having a first input terminal and a second input terminal and configured to amplify and/or compare signals on the first input terminal and the second input terminal;

a first switch;

a second switch;

a third switch;

a fourth switch;

a first capacitor, wherein an end of the first capacitor is coupled to the first input terminal, and other end of the first capacitor receives a first input voltage through the first switch;

a second capacitor, wherein an end of the second capacitor is coupled to the first input terminal, and other end of the second capacitor receives a first reference voltage through the second switch;

a third capacitor, wherein an end of the third capacitor is coupled to the second input terminal, and other end of the third capacitor receives a second input voltage through the third switch;

a fourth capacitor, wherein an end of the fourth capacitor is coupled to the second input terminal, and other end of the fourth capacitor receives a second reference voltage through the fourth switch, the second reference voltage being different from the first reference voltage; and

a fifth switch coupled between the first capacitor and the third capacitor, wherein the first capacitor and the third capacitor are electrically connected when the fifth switch is turned on.

2. The ADC of claim 1, wherein when the fifth switch is turned on, a node through which the first capacitor and the third capacitor are electrically connected is floating and not coupled or electrically connected to any voltage.

3. The ADC of claim 1, wherein a capacitance value of the first capacitor is substantially the same as a capacitance value of the third capacitor, and a capacitance value of the second capacitor is substantially the same as a capacitance value of the fourth capacitor.

4. The ADC of claim 1 further comprising:

a sixth switch coupled between the second capacitor and the fourth capacitor, wherein the second capacitor and the fourth capacitor are electrically connected when the sixth switch is turned on.

5. The ADC of claim 4, wherein when the sixth switch is turned on, a node through which the second capacitor and the fourth capacitor are electrically connected is floating and not coupled or electrically connected to any voltage.

6. An analog-to-digital converter (ADC) comprising:

an analog circuit having a first input terminal and a second input terminal and configured to amplify and/or compare signals on the first input terminal and the second input terminal;

a first switch;

a second switch;

a third switch;

a fourth switch;

a fifth switch;

a sixth switch;

a seventh switch;

an eighth switch;

a first capacitor, wherein an end of the first capacitor is coupled to the first input terminal, and other end of the first capacitor receives a first input voltage through the first switch or receives a first reference voltage through the third switch;

a second capacitor, wherein an end of the second capacitor is coupled to the first input terminal, and other end of the second capacitor receives a second reference voltage through the second switch or receives a third reference voltage through the fourth switch

a third capacitor, wherein an end of the third capacitor is coupled to the second input terminal, and other end of the third capacitor receives a second input voltage through the fifth switch or receives the first reference voltage through the seventh switch; and

a fourth capacitor, wherein an end of the fourth capacitor is coupled to the second input terminal, and other end of the fourth capacitor receives a fourth reference voltage through the sixth switch or receives the third reference voltage through the eighth switch.

7. The ADC of claim 6, wherein a capacitance value of the first capacitor is substantially the same as a capacitance value of the third capacitor, and a capacitance value of the second capacitor is substantially the same as a capacitance value of the fourth capacitor.

8. An analog-to-digital converter (ADC) comprising:

an analog circuit having a first input terminal and a second input terminal and configured to amplify and/or compare signals on the first input terminal and the second input terminal;

a first switch;

a second switch;

a third switch;

a fourth switch;

a first capacitor, wherein an end of the first capacitor is coupled to the first input terminal, and other end of the first capacitor receives a first input voltage through the first switch;

a second capacitor, wherein an end of the second capacitor is coupled to the first input terminal, and other end of the second capacitor receives a first reference voltage through the second switch;

a third capacitor, wherein an end of the third capacitor is coupled to the second input terminal, and other end of the third capacitor receives a second input voltage through the third switch;

a fourth capacitor, wherein an end of the fourth capacitor is coupled to the second input terminal, and other end of the fourth capacitor receives a second reference voltage through the fourth switch, the second reference voltage being different from the first reference voltage; and

a fifth switch coupled between the second capacitor and the fourth capacitor, wherein the second capacitor and the fourth capacitor are electrically connected when the fifth switch is turned on.

9. The ADC of claim 8, wherein when the fifth switch is turned on, a node through which the second capacitor and the fourth capacitor are electrically connected is floating and not coupled or electrically connected to any voltage.

10. The ADC of claim 8, wherein a capacitance value of the first capacitor is substantially the same as a capacitance value of the third capacitor, and a capacitance value of the second capacitor is substantially the same as a capacitance value of the fourth capacitor.