Voltage sensing type of matrix multiplication method for neuromorphic computing system

• US 10,635,398 B2
• Filed: 03/15/2018
• Issued: 04/28/2020
• Est. Priority Date: 03/15/2018
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Lin, Yu-Yu, Lee, Feng-Min
• Primary Examiner(s): Ngo, Chuong D
• Application Number:
  US15/922,359
• Publication Number:
  US 20190286419A1
• Time in Patent Office: 775 Days
• CPC Class Codes: G06F 17/16 Matrix or vector computation , e.g. matrix-matrix or matrix-vector multiplication, matrix factorization matrix transposition G06F7/78
• CPC Class Codes: G06F 2207/4802 Special implementations
• CPC Class Codes: G06F 2207/4814 Non-logic devices, e.g. operational amplifiers
• CPC Class Codes: G06F 7/5443 Sum of products for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00
• CPC Class Codes: G11C 11/54 using elements simulating biological cells, e.g. neuron
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0026 Bit-line or column circuits
• CPC Class Codes: G11C 13/0028 Word-line or row circuits
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 14/009 and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material
• CPC Class Codes: G11C 2213/31 Material having complex metal oxide, e.g. perovskite structure
• CPC Class Codes: G11C 2213/32 Material having simple binary metal oxide structure
• CPC Class Codes: G11C 2213/34 Material includes an oxide or a nitride
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: G11C 7/16 Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters

Abstract

A device for generating sum-of-products data includes an array of variable resistance cells, variable resistance cells in the array each including a transistor and a programmable resistor connected in parallel, the array including n columns of cells including strings of series-connected cells and m rows of cells. Control and bias circuitry are coupled to the array, including logic for programming the programmable resistors in the array with resistances corresponding to values of a weight factor W_mn for the corresponding cell. Alternatively, the resistances can be programmed during manufacture. Input drivers are coupled to corresponding ones of the m rows of cells, the input drivers selectively applying inputs X_m to rows m. Column drivers are configured to apply currents I_n to corresponding ones of the n columns of cells. Voltage sensing circuits operatively coupled to the columns of cells.

Claims

1. A device for generating sum-of-products, comprising:

an array of variable resistance cells, variable resistance cells in the array each comprising a transistor and a programmable resistor connected in parallel, the array including n columns of cells including strings of series-connected cells and m rows of cells, and the variable resistance cells programmable to store values of a weight factor R_mn for the corresponding cell;

m input drivers coupled to corresponding ones of the m rows of cells, the input drivers selectively applying inputs X_m to more than one of the m rows in parallel;

n column drivers applying currents I_n to corresponding ones of the n columns of cells to produce a voltage representing a sum-of-products of the inputs X_m applied to the more than one of the m rows and the weight factors R_mn for the cells; and

voltage sensing circuits operatively coupled to the n columns of cells to sense the voltages representing the sums of products.

2. The device of claim 1, wherein the programmable resistor in the variable resistance cell comprises a buried implant resistor in the transistor, programmed by an implant doping profile.

3. The device of claim 1, including control and bias circuitry coupled to the array, and including logic for programming the programmable resistors in the array with resistances corresponding to values of the weight factor R_mn for the corresponding cell.

4. The device of claim 1, wherein the programmable resistors in the variable resistance cells comprise phase change elements.

5. The device of claim 1, wherein the programmable resistors in the variable resistance cells comprise metal oxide elements.

6. The device of claim 1, wherein the programmable resistors in the variable resistance cells comprise conductive bridge elements.

7. The device of claim 1, wherein the programmable resistors in the variable resistance cells comprise a memory cell, and a resistor in parallel with a second transistor, the second transistor having a gate connected to the memory cell.

8. The device of claim 1, wherein a string in the strings includes a plurality of sub-strings, with contacts between the sub-strings, and logic for programming is configured to isolate sub-strings during programming of cells in the string.

9. The device of claim 1, wherein:

the variable resistance cells in the array each comprise a diffusion region in a substrate having proximal and distal areas, a first leg between the proximal and distal areas and a second leg between the proximal and distal areas;

the first leg including a channel region, and including a gate conductor over the channel region of the first leg forming a cell transistor; and

the second leg having a resistance that is a function of a doping profile and layout profile of the second leg which forms a programmable cell resistor in parallel with the cell transistor.

10. The device of claim 1, wherein the variable resistance cells in the array each comprise:

a diffusion region having proximal and distal areas, and a channel region between the proximal and distal areas, and including a gate conductor over the channel region of forming a cell transistor; and

a current path from the proximal area to the distal area comprising a first interlayer conductor, a conductor in an overlying patterned conductor layer, a second interlayer conductor, and a programmable resistance memory element forming a programmable cell resistor in parallel with the cell transistor.

11. The device of claim 10, including control and bias circuitry coupled to the array, and including logic for programming the programmable resistance memory elements in the array with resistances corresponding to values R_mn for a corresponding cell.

12. A device for generating sum-of-products, comprising:

an array of variable resistance cells, variable resistance cells in the array each comprising a transistor and a programmable resistor connected in parallel, the array including n columns of cells including strings of series-connected cells and m rows of cells;

m input drivers coupled to corresponding ones of the m rows of cells, the input drivers selectively applying inputs X_m to rows m;

n column drivers applying currents I_n to corresponding ones of the n columns of cells; and

voltage sensing circuits operatively coupled to the n columns of cells, wherein the array includes a first reference column of cells configured to generate a low column reference voltage and a second reference column of cells configured to generate a high column reference voltage;

the device including;

a circuit to generate sensing reference voltages as a function of the high and low column reference voltages; and

wherein the voltage sensing circuits include comparators configured to compare voltages on selected columns of cells with the sensing reference voltages to generate outputs indicating voltage levels on the selected columns.

13. A method for operating an array of variable resistance cells, variable resistance cells in the array each comprising a transistor and a programmable resistor connected in parallel, the array including n columns of cells including strings of series-connected cells and m rows of cells, to produce sum-of-products data, comprising:

programming the programmable resistors in the array with resistances corresponding to values of a weight factor R_mn for corresponding cells;

selectively applying inputs X_m to more than one of the m rows in parallel;

applying currents I_n to corresponding ones of the n columns of cells to produce a voltage representing a sum-of-products of the inputs X_m applied to the more than one of the m rows and the weight factors R_mn for the cells; and

sensing voltages on one or more of then columns of cells to sense one or more of the voltages representing the sums of products.

14. A method for operating an array of variable resistance cells, variable resistance cells in the array each comprising a transistor and a programmed resistor connected in parallel, the array including n columns of cells including strings of series-connected cells and m rows of cells, to produce sum-of-products data, comprising:

selectively applying inputs X_m to more than one of the m rows in parallel;

applying currents I_n to corresponding ones of the n columns of cells to produce a voltage representing a sum-of-products of the inputs X_m applied to the more than one of the m rows and weight factors R_mn for the cells; and

sensing voltages on one or more of then columns of cells to sense one or more of the voltages representing the sums of products.