Transaction identification

• US 10,635,613 B2
• Filed: 04/11/2017
• Issued: 04/28/2020
• Est. Priority Date: 04/11/2017
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ross, Frank F., Walker, Robert M.
• Primary Examiner(s): Yi, David
• Assistant Examiner(s): Ahmed, Zubair
• Application Number:
  US15/484,744
• Publication Number:
  US 20180293000A1
• Time in Patent Office: 1,113 Days
• CPC Class Codes: G06F 11/0751 Error or fault detection not based on redundancy power supply failures G06F1/30; network fault management H04L41/06
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00
• CPC Class Codes: G06F 11/141 for bus or memory accesses
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: H04L 1/00 Arrangements for detecting or preventing errors in the information received correcting synchronisation H04L7/00

Abstract

The present disclosure includes apparatuses and methods related to transaction identification. An example apparatus can determine a transaction identification (TID) associated with a command by comparing a host transaction identification (TID) record with a memory device transaction identification (TID) record.

Claims

1. An apparatus, comprising:

a memory device including a buffer; and

a host device coupled to the memory device, wherein the host device includes a host controller configured to;

determine a corrupt transaction identification (TID) associated with a command by comparing a host transaction identification (TID) record including host transaction identifications (TIDs) transmitted to the host device from the memory device and stored in the host controller of the host device with a memory device transaction identification (TID) record stored in the buffer, wherein a memory device transaction identification (TID) corresponding to a host transaction identification (TID) missing from the host TID record is the corrupt TID associated with the command; and

output the memory device TID associated with the command from the host device to the memory device in response to determining the corrupt TID associated with the command.

2. The apparatus of claim 1, wherein the host device is configured to send the command to the memory device.

3. The apparatus of claim 1, wherein the host is configured to generate transaction identifications (TIDs) as identifiers.

4. The apparatus of claim 1, wherein the host is configured to determine a transmission error based on an error detection scheme used in a TID transmission.

5. The apparatus of claim 1, wherein the memory device is a non-volatile dual in-line memory module (NVDIMM).

6. An apparatus, comprising:

a memory device including a buffer; and

a host device coupled to the memory device, wherein the host device includes a host controller configured to;

query the memory device with a status request in response to receiving a transmission error associated with a command;

receive a memory device transaction identification (TID) record from the buffer in the memory device;

determine a corrupt transaction identification (TID) associated with the command by comparing a host transaction identification (TID) record including host transaction identifications (TIDs) transmitted from the memory device to the host device and stored in the host controller of the host device with the memory device TID record, wherein a memory device transaction identification (TID) corresponding to a host transaction identification (TID) missing from the host TID record is the corrupt TID associated with the command; and

output the memory device TID associated with the command from the host device to the memory device in response to determining the corrupt TID associated with the command.

7. The apparatus of claim 6, wherein the memory device is configured to send the memory device TID record in response to receiving the query.

8. The apparatus of claim 6, wherein the memory device TID associated with the command is an implicit TID generated by the host device and the memory device simultaneously.

9. The apparatus of claim 6, wherein the memory device is configured to execute operations in an order that is different from an order in which the commands are received by the memory device.

10. An apparatus, comprising:

a memory device including a buffer; and

a host device coupled to the memory device, wherein the host device includes a host controller configured to;

receive data with a command from the memory device;

detect a transmission error in the data associated with the command;

query the memory device in response to receiving the transmission error;

receive a memory device transaction identification (TID) record from the buffer in the memory device;

determine a corrupt transaction identification (TID) associated with the command by comparing a host transaction identification (TID) record including host transaction identifications (TIDs) transmitted from the memory device to the host device and stored in the host controller of the host device with the memory device TID record, wherein a memory device transaction identification (TID) corresponding to a host transaction identification (TID) missing from the host TID record is the corrupt TID associated with the command; and

output the memory device TID associated with the command from the host device to the memory device in response to determining the corrupt TID associated with the command.

11. The apparatus of claim 10, wherein the query is a status request command.

12. The apparatus of claim 10, wherein the query is a mode register read command for the memory device TID record.

13. The apparatus of claim 10, wherein the buffer stores the memory device TID record for a set period of time.

14. The apparatus of claim 13, wherein a size of the buffer is based on the speed of transactions from the host device to the memory device.

15. The apparatus of claim 10, wherein the transmission error includes the corrupt TID.

16. The apparatus of claim 10, wherein the host device is configured to receive the data with the command from the memory device after the host device sends a command to the memory device.

17. A method, comprising:

generating first and second transaction identifications (TIDs), the first and second TIDs corresponding to first and second commands, respectively;

sending the first command with the first TID to a memory device;

sending the second command with the second TID to the memory device;

storing the first and second TIDs in a buffer in the memory device;

providing a first output data from the memory device to a host, the first output data comprising a first operation result based on the first command and a third transaction identification (TID) accompanied with the first operation result, the third TID corresponding to the first TID;

providing a second output data from the memory device to the host, the second output data comprising a second operation result based on the second command and a fourth transaction identification (TID) accompanied with the second operation result, the fourth TID corresponding to the second TID;

storing the third and fourth TIDs in a host controller of the host;

providing a memory device transaction identification (TID) record from the memory device to the host, wherein the memory device TID record includes the first and second TIDs;

comparing the third and fourth TIDs to the first and second TIDs to identify the third TID or the fourth TID including a transmission error; and

sending the first command with the first TID from the host to the memory device responsive to the third TID including the transmission error or sending the second command with the second TID from the host to the memory device responsive to the fourth TID including the transmission error.

18. The method of claim 17, wherein each of the first command and the second command is a read operation command.

19. The method of claim 17, wherein the third TID is outputted earlier than the first operation result from the memory device and the fourth TID is outputted earlier than the second operation result from the memory device.

20. The method of claim 17, wherein comparing the third and fourth TIDs to the outputted first and second TIDs is executed in a host.

21. A method, comprising:

receiving a transmission error associated with a command from a memory device including a buffer;

querying the memory device in response to receiving the transmission error;

receiving a memory device transaction identification (TID) record from the buffer in the memory device;

determining a corrupt transaction identification (TID) associated with the command by identifying a transaction identification (TID) in the memory device TID record corresponding to a host transaction identification (TID) that is missing from a host transaction identification (TID) record by comparing the memory device TID record with the host TID record, wherein the host TID record includes host transaction identifications (TIDs) transmitted to a host device from the memory device and stored in a host controller of the host device; and

outputting the memory device TID associated with the command from the host device to the memory device in response to determining the corrupt TID associated with the command.

22. The method of claim 21, wherein querying the memory device comprises using a status request command.

23. The method of claim 21, wherein querying the memory device comprises using a mode register command for the memory device TID record.

24. The method of claim 21, further comprising executing operations in an order that is different from an order in which the commands are received by the memory device.

25. The method of claim 21, further comprising storing the memory device TID record for a set period of time.

26. The method of claim 25, further comprising setting a size of the buffer based on speed of transactions from a host device to the memory device.