Enhanced NVDIMM architecture

• US 10,636,455 B2
• Filed: 07/12/2018
• Issued: 04/28/2020
• Est. Priority Date: 07/12/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Kosuru, Trinadhachari, Swaminathan, Janani, Sethuraman, Saravanan, McPadden, Adam J.
• Primary Examiner(s): Yi, David
• Assistant Examiner(s): Fulford, Dustin B.
• Application Number:
  US16/033,385
• Publication Number:
  US 20200020360A1
• Time in Patent Office: 656 Days
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0685 Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/1693 Timing circuits or methods
• CPC Class Codes: G11C 13/0033 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0061 Timing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 2013/0088 Write with the simultaneous writing of a plurality of cells
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 7/1045 : Read-write mode select circuits

Abstract

Aspects of the present disclosure relate to a memory module having a volatile memory, a high speed non-volatile memory, and a non-volatile memory. The memory module can allow write mirroring to the volatile memory and high speed non-volatile memory simultaneously. An I/O request is received. A determination is made whether the I/O request is a write or a read. In response to determining that the I/O request is a read, data included in the high speed non-volatile memory is transferred to the non-volatile memory. In response to determining that the I/O request is a write, at least one location to write data of the write is determined based on decoding bits of the write command. The data of the write can then be written to the at least one location.

Claims

1. A system comprising:

a non-volatile dual in-line memory module including a volatile memory, a high speed non-volatile memory (high speed NVM), and a non-volatile memory; and

one or more processing circuits, wherein the one or more processing circuits are configured to perform a method comprising;

receiving an I/O request;

determining whether the I/O request is a write or a read;

in response to determining that the I/O request is a read,

transferring data included in the high speed non-volatile memory to the non-volatile memory;

in response to determining that the I/O request is a write,

determining at least one location to write data of the write based on decoding bits of the write; and

writing, based on the decoded bits, the data of the write to the at least one location.

2. The system of claim 1, wherein the I/O request is the write, wherein determining at least one location to write data of the write based on decoding bits of the write and writing the data of the write to the at least one location comprises:

determining, based on the decoded bits, that the data of the write should be written to the volatile memory and high speed NVM simultaneously; and

writing the data of the write to the volatile memory and high speed NVM simultaneously.

3. The system of claim 1, wherein the at least one location to write the data of the write is the high speed NVM, wherein prior to writing the data to the high speed NVM, the one or more processing circuits are configured to:

determine whether data of the high speed NVM is to be transferred to the non-volatile memory;

copy, in response to determining that the data of the high speed NVM is to be transferred to the non-volatile memory, the data of the high speed NVM from the high speed NVM to the non-volatile memory; and

erase, in response to copying the data to the non-volatile memory, the data from the high speed NVM.

4. The system of claim 3, wherein the determining whether the data of the high speed NVM is to be transferred to the non-volatile memory includes:

determining an amount of memory occupied in the high speed NVM;

comparing the amount of memory to a memory threshold; and

determining, in response to the amount of memory exceeding the memory threshold, that the data is to be transferred from the high speed NVM to the non-volatile memory.

5. The system of claim 3, wherein the determining whether the data of the high speed NVM is to be transferred to the non-volatile memory includes:

determining, by referencing one or more temperature sensors on the memory module, a temperature of the memory module;

comparing the temperature of the memory module to a temperature threshold; and

determining, in response to the temperature of the memory module exceeding the temperature threshold, that the data is to be transferred from the high speed NVM to the non-volatile memory.

6. The system of claim 1, wherein the I/O request is the write, wherein determining at least one location to write data of the write based on decoding bits within the write and writing the data of the write to the at least one location comprises:

determining, based on the decoded bits, that the data of the write should be written to high speed NVM;

determining whether data of the high speed NVM is to be transferred to the non-volatile memory;

copying, in response to determining that the data of the high speed NVM is to be transferred to the non-volatile memory, the data of the high speed NVM from the high speed NVM to the non-volatile memory;

erasing, in response to copying the data to the non-volatile memory, the data from the high speed NVM; and

writing the data of the write to the volatile memory and high speed non-volatile memory simultaneously.

7. The system of claim 1, wherein the volatile memory is dynamic random access memory (DRAM), wherein the high speed NVM is 3D XPoint memory, wherein the non-volatile memory is flash memory.

8. A method for maintaining persistence on a non-volatile dual in-line memory module, the memory module including at least one volatile memory, at least one high speed non-volatile memory (NVM) and at least one non-volatile memory, the method comprising:

receiving a write request;

decoding bits of the write request;

determining, based on the decoded bits, that data of the write request should be mirrored to the at least one high speed NVM and the at least one volatile memory simultaneously;

determining, in response to determining that the data of the write request should be mirrored to the at least one high speed NVM and the at least one volatile memory simultaneously, that data of the at least one high speed NVM should be transferred to the at least one non-volatile memory and flushed;

transferring, in response to determining that the data of the at least one high speed NVM should be transferred to the non-volatile memory, data from the at least one high speed NVM to the at least one non-volatile memory;

flushing, in response to transferring the data of the at least one high speed NVM to the at least one non-volatile memory, the data from the at least one high speed NVM; and

writing, in response to flushing the data from the at least one high speed NVM, the data of the write request to the at least one high speed NVM and the at least one volatile memory simultaneously.

9. The method of claim 8, wherein the non-volatile dual in-line memory module includes two high speed NVM'"'"'s, wherein prior to writing, a determination is made which of the two high speed NVM'"'"'s to write data of the write request to, the determination comprising:

determining a first amount of memory stored in a first high speed NVM of the two high speed NVM'"'"'s;

determining a second amount of memory stored in a second high speed NVM of the two high speed NVM'"'"'s;

comparing the first amount of memory stored in the first high speed NVM with the second amount of memory stored in the second high speed NVM; and

determining, in response to the first amount of memory stored in the first high speed NVM being less than the second amount of memory stored in the second high speed NVM, that the data of the write request should be written to the first high speed NVM and not the second high speed NVM, where writing includes writing data of the write request to the first high speed NVM and the at least one volatile memory simultaneously.

10. The method of claim 8, wherein the non-volatile dual in-line memory module includes two high speed NVM'"'"'s, wherein prior to writing, a determination is made which of the two high speed NVM'"'"'s to write data of the write request to, the determination comprising:

determining a first amount of memory stored in a first high speed NVM of the two high speed NVM'"'"'s;

determining a second amount of memory stored in a second high speed NVM of the two high speed NVM'"'"'s;

comparing the first amount of memory stored in the first high speed NVM to a memory threshold;

comparing the second amount of memory stored in the second high speed NVM to the memory threshold;

determining, based on the comparisons, that the first amount of memory stored in the first high speed NVM satisfies the memory threshold and that the second amount of memory stored in the second high speed NVM exceeds the memory threshold; and

determining, in response to the first amount of memory stored in the first high speed NVM satisfying the memory threshold and the second amount of memory stored in the second high speed NVM exceeding the memory, that the data of the write request should be written to the first high speed NVM and not the second high speed NVM, where writing includes writing data of the write request to the first high speed NVM and the at least one volatile memory simultaneously.

11. The method of claim 8, wherein the non-volatile dual in-line memory module includes two high speed NVM'"'"'s, wherein determining that data of the at least one high speed NVM should be transferred to the at least one non-volatile memory and flushed comprises:

determining a first amount of memory stored in a first high speed NVM of the two high speed NVM'"'"'s;

determining a second amount of memory stored in a second high speed NVM of the two high speed NVM'"'"'s;

comparing the first amount of memory stored in the first high speed NVM with the second amount of memory stored in the second high speed NVM; and

determining, based on the first amount of memory stored in the first high speed NVM being higher than the second amount of memory stored in the second high speed NVM, that the first amount of memory stored in the first high speed NVM should be transferred to the at least one non-volatile memory and flushed and that the second amount of memory stored in the second high speed NVM should not be transferred to the at least one non-volatile memory.

12. The method of claim 8, wherein determining that the data of the high speed NVM should be transferred to the non-volatile memory and flushed includes:

determining, by referencing one or more voltage sensors on the memory module, a voltage of the memory module;

comparing the voltage of the memory module to a voltage threshold; and

determining, in response to the voltage of the memory module exceeding the voltage threshold, that the data of the at least one high speed NVM is to be transferred from the high speed NVM to the non-volatile memory.

13. The method of claim 8, further comprising:

receiving a second write request;

decoding bits of the second write request;

determining, based on the decoded bits of the second write request, that data of the second write request should be written to the at least one high speed NVM only; and

writing the data of the second write request to the at least on high speed NVM.

14. The method of claim 8, further comprising:

monitoring for an I/O request;

determining whether the I/O request is a write request or a read request; and

transferring, in response to determining that the I/O request is the read request, data of the at least one high speed NVM to the at least one non-volatile memory.

15. A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform a method for maintaining persistence on a non-volatile dual in-line memory module, the memory module including at least one volatile memory, at least one high speed non-volatile memory (NVM) and at least one non-volatile memory, the method comprising:

receiving a write request;

decoding bits of the write request;

determining, based on the decoded bits, that data of the write request should be mirrored to the at least one high speed NVM and the at least one volatile memory simultaneously;

determining, in response to determining that the data of the write request should be mirrored to the at least one high speed NVM and the at least one volatile memory simultaneously, that data of the at least one high speed NVM should be transferred to the at least one non-volatile memory and flushed;

transferring, in response to determining that the data of the at least one high speed NVM should be transferred to the non-volatile memory, data from the at least one high speed NVM to the at least one non-volatile memory;

flushing, in response to transferring the data of the at least one high speed NVM to the at least one non-volatile memory, the data from the at least one high speed NVM; and

writing, in response to flushing the data from the at least one high speed NVM, the data of the write request to the at least one high speed NVM and the at least one volatile memory simultaneously.

16. The computer program product of claim 15, wherein the method performed by the processor further comprises:

receiving a second write request;

decoding bits of the second write request;

determining, based on the decoded bits of the second write request, that data of the second write request should be written to the at least one high speed NVM only; and

writing the data of the second write request to the at least one high speed NVM.

17. The computer program product of claim 15, wherein the method performed by the processor further comprises:

monitoring for an I/O request;

determining whether the I/O request is a write request or a read request; and

transferring, in response to determining that the I/O request is the read request, data of the at least one high speed NVM to the at least one non-volatile memory.

18. The computer program product of claim 15, wherein the method performed by the processor further comprises:

monitoring for an I/O request to determine whether the I/O request is received at a first time;

transferring, in response to determining that the I/O request is not received at the first time, data of the at least one high speed NVM to the at least one non-volatile memory.

19. The computer program product of claim 16, wherein the non-volatile dual in-line memory module includes two high speed NVM'"'"'s, wherein prior to writing, a determination is made which of the two high speed NVM'"'"'s to write data of the write request to, the determination comprising:

determining a first amount of memory stored in a first high speed NVM of the two high speed NVM'"'"'s;

determining a second amount of memory stored in a second high speed NVM of the two high speed NVM'"'"'s;

comparing the first amount of memory stored in the first high speed NVM with the second amount of memory stored in the second high speed NVM; and

determining, in response to the first amount of memory stored in the first high speed NVM being less than the second amount of memory stored in the second high speed NVM, that the data of the write request should be written to the first high speed NVM and not the second high speed NVM, where writing includes writing data of the write request to the first high speed NVM and the at least one volatile memory simultaneously.

20. The computer program product of claim 15, wherein the volatile memory is dynamic random access memory (DRAM), wherein the high speed NVM is 3D XPoint memory, and wherein the non-volatile memory is flash memory.