Semiconductor fins with dielectric isolation at fin bottom

• US 10,636,709 B2
• Filed: 04/10/2018
• Issued: 04/28/2020
• Est. Priority Date: 04/10/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Xu, Peng, Cheng, Kangguo, Strane, Jay W.
• Primary Examiner(s): Amer, Mounir S
• Application Number:
  US15/949,602
• Publication Number:
  US 20190311955A1
• Time in Patent Office: 749 Days
• Field of Search: None
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/1079 with insulated gate
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66469 with one- or zero-dimensional channel, e.g. quantum wire field-effect transistors, in-plane gate transistors [IPG], single electron transistors [SET], Coulomb blockade transistors, striped channel transistors
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET

Abstract

A method is presented for forming dielectric isolated fins. The method includes forming a plurality of fin structures over a semiconductor substrate, forming spacers adjacent each of the plurality of fins, recessing the semiconductor substrate to form bottom fin profiles, and forming shallow trench isolation (STI) regions between the plurality of fins and the bottom fin profiles. The method further includes etching the STI regions, a select number of the plurality of fins, and a portion of a select number of the bottom fin profiles to create cavities between a mechanical anchor defined between a pair of fins of the plurality of fins, the etching resulting in undercutting of remaining fins.

Claims

1. A method for forming dielectric isolated fins, the method comprising:

forming a plurality of fins over a semiconductor substrate;

forming spacers adjacent each of the plurality of fins;

recessing the semiconductor substrate to form bottom fin profiles;

forming shallow trench isolation (STI) regions between the plurality of fins and the bottom fin profiles; and

etching the STI regions, a select number of the plurality of fins, and a portion of a select number of the bottom fin profiles to create cavities on opposed ends of a mechanical anchor defined between a pair of fins of the plurality of fins, the etching resulting in undercutting of remaining fins.

2. The method of claim 1, further comprising filling the cavities with a dielectric.

3. The method of claim 2, further comprising recessing the dielectric to expose the spacers, the recessing of the dielectric resulting in an irregular-shaped dielectric profile.

4. The method of claim 3, further comprising stripping the spacers to expose the plurality of fins over the irregular-shaped dielectric profile.

5. The method of claim 1, wherein the bottom fin profiles are tapered.

6. The method of claim 1, wherein the etching is performed in three stages.

7. The method of claim 1, wherein each of the plurality of fins is formed from a nanosheet stack.

8. A method for forming dielectric isolated fins, the method comprising:

forming a plurality of fins over a semiconductor substrate;

recessing the semiconductor substrate to form tapered bottom fin profiles;

forming shallow trench isolation (STI) regions between the plurality of fins and the tapered bottom fin profiles; and

undercutting the plurality of fins via a three-stage etch process, the third etch extending laterally and resulting in removal of bottom sections of the plurality of fins.

9. The method of claim 8, further comprising forming spacers adjacent each of the plurality of fins.

10. The method of claim 9, further comprising creating cavities between a mechanical anchor defined between a pair of fins of the plurality of fins.

11. The method of claim 10, further comprising depositing a mask over a select number of the plurality of fins to create the mechanical anchor.

12. The method of claim 11, wherein the mechanical anchor is an oxide pillar.

13. The method of claim 11, further comprising filling the cavities with a dielectric.

14. The method of claim 13, further comprising recessing the dielectric to expose the spacers, the recessing of the dielectric resulting in an irregular-shaped dielectric profile.

15. The method of claim 14, further comprising stripping the spacers to expose the plurality of fins over the irregular-shaped dielectric profile.

16. The method of claim 8, wherein the undercutting of the plurality of fins results in a non-linear bottom surface for each of the plurality of fins.