System and method to enhance solder joint reliability

• US 10,636,722 B2
• Filed: 09/26/2017
• Issued: 04/28/2020
• Est. Priority Date: 09/26/2017
• Status: Active Grant

• Current Assignee: JP Morgan Chase Bank, N.A. (JP Morgan Chase & Co)
• Original Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Inventors: Yu, Lee Kong, Im, Sungjun, Lau, Chun Sean, Chin, Yoong Tatt, Gill, Paramjeet Singh, Teh, Weng-Hong
• Primary Examiner(s): Pham, Long
• Application Number:
  US15/715,863
• Publication Number:
  US 20190096783A1
• Time in Patent Office: 945 Days
• Field of Search: None
• CPC Class Codes: H01L 21/4871 Bases, plates or heatsinks
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 2224/05 of an individual bonding area
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05181 Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/13101 the principal constituent melting at a temperature of less than 400°C
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/81385 Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/81395 having an external coating, e.g. protective bond-through coating
• CPC Class Codes: H01L 2224/81815 Reflow soldering
• CPC Class Codes: H01L 2224/81908 involving monitoring, e.g. feedback loop
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/3171 the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 23/3185 the coating covering also the sidewalls of the semiconductor body
• CPC Class Codes: H01L 23/3675 characterised by the shape of the housing
• CPC Class Codes: H01L 23/3736 Metallic materials H01L23/3732, H01L23/3733, H01L23/3735, H01L23/3737, H01L23/3738 take precedence
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/16151 : Cap comprising an aperture, e.g. for pressure control, encapsulation
• CPC Class Codes: H01L 2924/16195 : Flat cap [not enclosing an internal cavity]
• CPC Class Codes: H01L 2924/16235 : Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip
• CPC Class Codes: H01L 2924/3512 : Cracking

Abstract

A reliability cover that is disposed over at least one of an integrated circuit package and a Si die of the integrated circuit package is disclosed. The integrated circuit package is mountable to a printed circuit board via a plurality of solder balls. The reliability cover is configured to reduce a difference in a coefficient of thermal expansion between the integrated circuit package and the printed circuit board, and between the Si die and a substrate of the integrated circuit package by a threshold value.

Claims

1. A system, comprising:

a reliability cover disposed over at least one of an integrated circuit package and a Si die of the integrated circuit package, wherein the integrated circuit package is mountable to a printed circuit board via a plurality of solder balls, wherein the reliability cover is disposed over the Si die, wherein the reliability cover covers only one or more portions of a top surface area of the Si die, rather than covering the entire top surface area of the Si die,

wherein the reliability cover is configured to reduce a difference in a coefficient of thermal expansion between the integrated circuit package and the printed circuit board, or between the Si die and a substrate of the integrated circuit package by a threshold value, and

wherein the reliability cover is disposed at one or more corners of a top surface of the at least one of the integrated circuit package and the Si die of the integrated circuit package.

2. The system of claim 1, wherein the reliability cover is deposited as a film.

3. The system of claim 1, wherein the reliability cover is configured as a mechanical lid.

4. The system of claim 1, wherein the reliability cover is disposed along at least a portion of a perimeter of the top surface of the at least one of the integrated circuit package and the Si die of the integrated circuit package.

5. The system of claim 1, wherein the reliability cover is disposed over areas of the integrated circuit package that correspond to a failure profile of solder joints formed between the plurality of solder balls and the integrated circuit package and between the plurality of solder balls and the printed circuit board.

6. The system of claim 1, wherein the reliability cover comprises one or more reliability cover portions, and each of the one or more reliability cover portions is configured to reduce the difference in the coefficient of thermal expansion between the integrated circuit package and the printed circuit board by varying threshold values.

7. The system of claim 1, wherein the reliability cover comprises a package level reliability cover that is disposed on at least a portion of the integrated circuit package, and wherein the reliability cover further comprises a die level reliability cover that is disposed on at least a portion of the Si die.

8. The system of claim 1, wherein the reliability cover comprises a die level reliability cover that is disposed on an interposer layer formed between a substrate of the integrated circuit package and the Si die.

9. The system of claim 1, wherein the reliability cover is composed of at least one of a copper alloy and an aluminum alloy.

10. The system of claim 1, wherein a thickness of the reliability cover is scaled based on a height of the integrated circuit package, a coefficient of thermal expansion of the integrated circuit package, and a coefficient of thermal expansion of the reliability cover.

11. The system of claim 1, further comprising an air release hole on a surface of the reliability cover to vent air pressure from between the reliability cover and the integrated circuit package.

14. The system of claim 1, wherein the top surface area of the Si die has a perimeter, and the reliability cover does not extend to at least a portion of the perimeter.

15. The system of claim 1, wherein the reliability cover does not cover a side area of the Si die.

12. A system, comprising:

a printed circuit board having a first coefficient of thermal expansion;

an integrated circuit package configured to be mounted to the printed circuit board and having a second coefficient of thermal expansion; and

a reliability cover disposed over at least a portion of the integrated circuit package and at least a portion of a Si die within the integrated circuit package, wherein the reliability cover does not cover a side area of the Si die and wherein the reliability cover is configured to reduce a difference between the first coefficient of thermal expansion and the second coefficient of thermal expansion by a threshold value,

wherein a second reliability cover is disposed over the integrated circuit package, and the second reliability cover does not cover a side area of the integrated circuit package.

13. The system of claim 12, further comprising a plurality of solder balls configured to mount the integrated circuit package to the printed circuit board, wherein at least some of the plurality of solder balls are attached to a preform provided on a surface of the printed circuit board, and wherein a combined height of each of the at least some of the plurality of solder balls and the preform is greater than a height of each of the at least some of the plurality of solder balls.

16. The system of claim 12, wherein the reliability cover does not cover a side area of the integrated circuit package.

17. The system of claim 12, wherein the reliability cover does not cover at least a portion of a top surface area of the Si die.

18. The system of claim 12, wherein the reliability cover does not cover any part of all side areas of the integrated circuit package.