Formation of fine pitch traces using ultra-thin PAA modified fully additive process

• US 10,636,734 B2
• Filed: 08/22/2019
• Issued: 04/28/2020
• Est. Priority Date: 02/02/2018
• Status: Active Grant

• Current Assignee: Compass Technology Company, Limited
• Original Assignee: Compass Technology Company, Limited
• Inventors: Pun, Kelvin Po Leung, Cheung, Chee Wah
• Primary Examiner(s): Sullivan, Caleen O
• Application Number:
  US16/548,373
• Publication Number:
  US 20190385936A1
• Time in Patent Office: 250 Days
• Field of Search: 257762, 174260
• CPC Class Codes: B23K 2101/40 Semiconductor devices
• CPC Class Codes: B23K 2103/42 Plastics B23K2103/16 takes precedence
• CPC Class Codes: B23K 26/382 by boring
• CPC Class Codes: B23K 26/384 of specially shaped holes
• CPC Class Codes: B23K 26/402 involving non-metallic material, e.g. isolators
• CPC Class Codes: C23C 18/1653 Two or more layers with at least one layer obtained by electroless plating and one layer obtained by electroplating
• CPC Class Codes: C23C 18/1692 Heat-treatment
• CPC Class Codes: C23C 18/2086 with use of organic or inorganic compounds other than metals, first
• CPC Class Codes: C23C 18/30 Activating or accelerating or sensitising with palladium or other noble metal
• CPC Class Codes: C23C 18/36 using hypophosphites
• CPC Class Codes: C23C 18/50 with alloys based on iron, cobalt or nickel
• CPC Class Codes: C23C 18/54 Contact plating, i.e. electroless electrochemical plating
• CPC Class Codes: C25D 3/38 of copper
• CPC Class Codes: C25D 5/022 using masking means
• CPC Class Codes: C25D 5/12 at least one layer being of nickel or chromium
• CPC Class Codes: C25D 5/611 Smooth layers
• CPC Class Codes: C25D 5/617 Crystalline layers
• CPC Class Codes: C25D 7/00 Electroplating characterised by the article coated
• CPC Class Codes: G03F 7/039 Macromolecular compounds which are photodegradable, e.g. positive electron resists G03F7/075 takes precedence; macromolecular quinonediazides G03F7/023
• CPC Class Codes: G03F 7/16 Coating processes; Apparatus therefor applying coatings to base materials in general B05; applying photosensitive compositions to base for photographic purposes G03C1/74
• CPC Class Codes: G03F 7/20 : Exposure; Apparatus therefor photographic printing apparatus for making copies G03B27/00
• CPC Class Codes: G03F 7/26 : Processing photosensitive materials; Apparatus therefor G03F7/12 - G03F7/24 take precedence
• CPC Class Codes: G03F 7/40 : Treatment after imagewise removal, e.g. baking
• CPC Class Codes: H01L 21/4846 : Leads on or in insulating or insulated substrates, e.g. metallisation H01L21/4821 takes precedence; metallisation of ceramics in general C04B41/51; printed circuits H05K3/00
• CPC Class Codes: H01L 2224/16225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48227 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 23/145 : Organic substrates, e.g. plastic
• CPC Class Codes: H01L 23/49822 : Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 23/4985 : Flexible insulating substrates H01L23/49572 and H01L23/49855 take precedence
• CPC Class Codes: H01L 23/49866 : characterised by the materials materials of the substrates H01L23/14, of the lead-frames H01L23/49579
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00

Abstract

A method to produce a substrate suitable for diffusion bonding is described. A flexible dielectric substrate is provided. An alkaline modification is applied to the dielectric substrate to form a polyamic acid (PAA) anchoring layer on a surface of the dielectric substrate. A Ni—P seed layer is elecrolessly plated on the PAA layer. Copper traces are plated within a photoresist pattern on the Ni—P seed layer. A surface finishing layer is electrolytically plated on the copper traces. The photoresist pattern and Ni—P seed layer not covered by the copper traces are removed to complete the substrate suitable for diffusion bonding.

Claims

1. A method of manufacturing a flexible substrate comprising:

providing a flexible dielectric substrate comprising any kind of polyimide (PI), including Kapton PI or Upisel PI, modified PI (MPI), cyclo olefin polymer (COP), or liquid crystal polymer (LCP);

applying an alkaline modification to said dielectric substrate to form a polyamic acid (PAA) anchoring layer on a surface of said dielectric substrate;

electrolessly plating a Ni—

P seed layer on said PAA layer;

forming a photoresist pattern on said Ni—

P seed layer;

plating copper traces within said photoresist pattern;

plating a surface finishing layer on said copper traces; and

removing said photoresist pattern and etching away said Ni—

P seed layer not covered by said copper traces to complete said flexible substrate.

2. The method according to claim 1 wherein said alkaline modification comprises applying a KOH/alkaline base chemical to said dielectric substrate wherein said PAA layer has a thickness of less than 100 nm and preferably less than 10 nm.

3. The method according to claim 1 further comprising depositing a catalyst layer comprising Palladium (Pd) or Nickel (Ni) on said PAA layer by immersion into an ionic metal solution to activate said PAA layer for subsequent electroless Ni—

P seed layer plating.

4. The method according to claim 1 wherein said electrolessly plating said Ni—

P seed layer is an autocatalytic process and wherein said Ni—

P seed layer has a thickness of 0.1 μ

m +/−

10% and a composition of Ni;

96.5˜

97.5 wt % and P;

2.5˜

3.5 wt %.

5. The method according to claim 1 wherein said forming said photoresist pattern comprises:

applying a photoresist on said Ni—

P seed layer; and

exposing and developing said photoresist to form a pattern for fine pitch traces for circuitization.

6. The method according to claim 1 further comprising annealing said substrate after forming said Ni—

P seed layer preferably at 200°

C. for at least ten minutes to at most 2 hours.

7. The method according to claim 1 wherein said plating said copper traces comprises electrolytically plating copper to a thickness of between about 2 to 18 μ

m wherein a ratio of the top to bottom widths of said copper traces is close to 1, wherein an elongation strength of said copper traces is over 15%, wherein a tensile strength of said copper traces is between about 290 and 340 N/mm², and wherein a hardness of said copper traces is 100 in vicker hardness with a purity of more than 99.9%.

8. The method according to claim 1 wherein said surface finishing layer comprises immersion Tin, electrolytic Ni/Au, electroless Nickel/Immersion gold (ENIG), Electroless Nickel/Electroless Palladium/Immersion Gold (ENEPIG), electrolytic Palladium, electrolytic Titanium, electrolytic Tin, electrolytic Rhodium, Electroless Palladium/Autocatalytic Gold (EPAG), or Immersion Gold/Electroless Palladium/Immersion Gold (IGEPIG).

9. The method according to claim 1 further comprising:

laser drilling at least one first via opening all the way through said dielectric substrate wherein said applying said alkaline modification to said dielectric substrate, electrolessly plating said first Ni—

P seed layer, and forming said first photoresist pattern are performed on both top and bottom surfaces and wherein said plating first copper traces is within said first photoresist patterns and through said at least one first via opening.

10. The method of claim 9 further comprising:

laminating a bonding film on top and bottom surfaces of said first copper traces;

laminating a dielectric layer on top and bottom of said bonding films;

laser drilling at least one second via opening all the way through said dielectric layer and said bonding film to contact said first copper traces on top and bottom of said substrate;

thereafter applying an alkaline modification to said dielectric layers to form a second polyamic acid (PAA) anchoring layer on top and bottom surfaces of said dielectric layers and within said at least one second via openings;

electrolessly plating a second Ni—

P seed layer on top and bottom of said second PAA layers;

forming a second photoresist pattern on top and bottom of said second Ni—

P seed layers;

plating second copper traces within said second photoresist patterns and through said at least one second via opening;

plating a surface finishing layer on said second copper traces; and

removing said second photoresist patterns and etching away said second Ni—

P seed layers not covered by said second copper traces to complete said flexible substrate.

11. A chip on film comprising:

a flexible dielectric substrate having a first polyamic acid (PAA) anchoring layer on its top surface;

at least one first copper trace on a first Ni—

P seed layer on said first PAA layer and having a surface finishing layer on a top surface of said at least one first copper trace wherein said surface finishing layer comprises electrolytic Ni/Au, electroless Nickel/Immersion gold (ENIG), Electroless Nickel/Electroless Palladium/Immersion Gold (ENEPIG), electrolytic Palladium, electrolytic Titanium, immersion Tin, electrolytic Tin, electrolytic Rhodium, Electroless Palladium/Autocatalytic Gold (EPAG), or Immersion Gold/Electroless Palladium/Immersion Gold (IGEPIG); and

at least one die mounted on said dielectric substrate to said at least one first copper trace.

12. The chip on film according to claim 11 wherein said flexible dielectric layer comprises any kind of polyimide (PI), including Kapton PI or Upisel PI, modified PI (MPI), cyclo olefin polymer (COP), or liquid crystal polymer (LCP).

13. The chip on film according to claim 11 further comprising:

a second PAA layer on a bottom surface of said dielectric substrate; and

at least one second copper trace on a second Ni—

P seed layer on said second PAA layer wherein said first and second copper traces are interconnected by through a copper via through said dielectric substrate wherein said copper via further comprises a third PAA layer contacting said dielectric substrate and a third Ni—

P seed layer between said third PAA layer and said copper via.

14. The chip on film according to claim 13 wherein said first and second PAA layers have a thickness of less than 100 nm and preferably less than 10 nm.

15. The chip on film according to claim 13 wherein said first and second Ni—

P seed layers have a thickness of 0.1 μ

m +/−

10%, a surface roughness with Ra value below 100 nm, and a composition of Ni;

96.5˜

97.5 wt % and P;

2.5˜

3.5 wt %.

16. The chip on film according to claim 13 wherein said at least one first copper trace and at least one second copper trace have a thickness of between about 2 to 18 μ

m wherein a ratio of the top to bottom widths of said at least one first copper trace and at least one second copper trace is close to 1, wherein an elongation strength of said at least one first copper trace is over 15%, wherein a tensile strength of said at least one first copper trace is between about 290 and 340 N/mm², and wherein a hardness of said at least one first copper trace and at least one second copper trace is 100 in vicker hardness with a purity of more than 99.9%.

17. The chip on film according to claim 13 wherein a center to center distance between two adjacent said first copper traces and between two adjacent said second copper traces is less than 8 μ

m.

18. The chip on film according to claim 13 wherein a second peel strength of said chip on film after reliability tests of low temperature storage, high temperature storage, moisture sensitivity level-3, and thermal shock is the same or greater than a first peel strength of said chip on film before said reliability tests.

19. The chip on film according to claim 13 further comprising:

a first bonding film over said at least one first copper trace and a second bonding film over said at least one second copper trace; and

an additional flexible dielectric substrate layer on said first and second bonding films and third and fourth at least one copper traces on third and fourth Ni—

P seed layers on third and fourth PAA anchoring layers on said third and fourth additional flexible dielectric substrate layers, respectively, wherein said at least one third and fourth copper traces are interconnected to underlying said first and second at least one copper traces, respectively, by second and third copper vias through said third and fourth additional PI or LCP layers and said first and second bonding layers, respectively, wherein said second and third copper vias further comprise a fourth PAA layer contacting said third and fourth additional flexible dielectric substrate layers and said first and second bonding layers, respectively, and a fourth Ni—

P seed layer between said fourth PAA layer and said second and third copper vias wherein said at least one die is mounted and bonded on a topmost of said at least one third or fourth copper trace.

20. The chip on film according to claim 19 further comprising any number of bonding layers, additional flexible dielectric substrate layers, and copper traces on top and bottom of said chip on film.