Apparatus and method to prevent integrated circuit from entering latch-up mode

• US 10,636,872 B1
• Filed: 10/31/2018
• Issued: 04/28/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Chang, Shunhua T., Gebreselasie, Ephrem G., Muhammad, Mujahid, Lu, Xiangxiang, Yu, Mickey H.
• Primary Examiner(s): Ha, Nathan W
• Application Number:
  US16/176,380
• Publication Number:
  US 20200135856A1
• Time in Patent Office: 545 Days
• CPC Class Codes: G09G 2330/04 Display protection
• CPC Class Codes: G09G 3/32 semiconductive, e.g. using light-emitting diodes [LED]
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/0921 Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0684 characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
• CPC Class Codes: H01L 29/1087 characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

The disclosure provides an apparatus for preventing an integrated circuit (IC) structure from entering a latch-up mode. In an embodiment, the apparatus may include: a p-type substrate; an n-well within the p-type substrate; an n-type region within the p-type substrate, the n-type region being distinct from the n-well; a p-type region within the n-well; a power supply electrically coupled to the p-type region within the n-well; and a directional diode electrically coupling the power supply to the n-well in parallel with the p-type region. The directional diode biases a current flow from the power supply to the n-well, and the directional diode contacts the n-well distal to the p-type region.

Claims

1. An apparatus for preventing an integrated circuit (IC) structure from entering a latch-up mode, the apparatus comprising:

a p-type substrate;

an n-well within the p-type substrate;

an n-type region within the p-type substrate, the n-type region being distinct from the n-well;

a p-type region within the n-well, wherein the n-well is free of n-type regions therein;

a power supply electrically coupled to the p-type region within the n-well; and

a directional diode directly electrically coupling the power supply to a metal contact within the n-well in parallel with the p-type region, wherein the directional diode biases a current flow from the power supply to the n-well, and wherein the directional diode contacts the n-well distal to the p-type region.

2. The apparatus of claim 1, wherein a horizontal separation between the n-type region and the p-type region is at least fifty micrometers (μ

m).

3. The apparatus of claim 1, further comprising a shallow trench isolation (STI) over the n-well between the p-type region and the directional diode.

4. The apparatus of claim 1, wherein the n-type region within the p-type substrate includes a first n-type terminal electrically coupled to ground, and a second n-type terminal electrically coupled to the p-type region within the n-well.

5. The apparatus of claim 1, wherein the n-type region comprises a pair of n-type terminals of a first device, and wherein the p-type region comprises a pair of p-type terminals of a second device distinct from the first device.

6. The apparatus of claim 1, wherein the directional diode comprises a diode-connected transistor or a Schottky diode.

7. The apparatus of claim 1, wherein the n-type region and the p-type region are each electrically coupled to an inverter circuit or a driver circuit.

8. An apparatus for preventing an integrated circuit (IC) structure from entering a latch-up mode, the apparatus comprising:

a p-type substrate;

an n-well within the p-type substrate;

an n-type region within the p-type substrate, the n-type region being distinct from the n-well, wherein the n-type region is electrically coupled to ground;

a p-type region within the n-well, wherein the n-well is free of n-type regions therein; and

a directional diode directly electrically coupling a metal contact within the p-type substrate to ground in parallel with the n-type region, wherein the directional diode biases a current flow from the p-type substrate to ground, and wherein the directional diode contacts the p-type substrate distal to the n-type region.

9. The apparatus of claim 8, wherein a horizontal separation between the n-type region the p-type region is at least fifty micrometers (μ

m).

10. The apparatus of claim 8, further comprising a shallow trench isolation (STI) over the p-type substrate between the n-type region and the directional diode.

11. The apparatus of claim 8, wherein the p-type region substrate includes a first p-type terminal electrically coupled to a power supply, and a second n-type terminal electrically coupled to the n-type region within the p-type substrate.

12. The apparatus of claim 10, wherein the n-type region comprises a pair of n-type terminals of a first device, and wherein the p-type region comprises a pair of p-type terminals of a second device distinct from the first device.

13. The apparatus of claim 8, wherein the directional diode comprises a diode-connected transistor or a Schottky diode.

14. The apparatus of claim 8, wherein the n-type region and the p-type region are each electrically coupled to an inverter circuit or a driver circuit.

15. An apparatus for preventing an integrated circuit (IC) structure from entering a latch-up mode, the apparatus comprising:

a p-type substrate;

an n-well within the p-type substrate;

a first device formed over the p-type substrate, and a pair of n-type terminals within the p-type substrate, wherein the p-type substrate is free of p-type regions therein;

a second device formed over the n-well, and a pair of p-type terminals within the n-well, wherein the n-well is free of n-type regions therein;

a first shallow trench isolation (STI) on the p-type substrate and the n-well, and between the first and second devices;

a power supply electrically coupled to one of the pair of p-type terminals of the second device;

a directional diode electrically directly coupling the power supply to a metal contact within the n-well in parallel with the one of the pair of p-type terminals of the second device, wherein the directional diode biases a current flow from the power supply to the n-well, and wherein the directional diode contacts the n-well distal to the second device; and

a second shallow trench isolation (STI) over the n-well between the second transistor and the directional diode.

16. The apparatus of claim 15, wherein a horizontal width of the first STI is at least fifty micrometers (μ

m).

17. The apparatus of claim 15, wherein one of the pair of n-type terminals of the first device is electrically coupled to ground.

18. The apparatus of claim 17, further comprising:

a signal input line coupled to the first device in parallel with the gate of the second device; and

a signal output line coupled to one of the pair of n-type terminals of the first device in parallel with one of the pair of p-type terminals of the second device.

19. The apparatus of claim 15, wherein the directional diode comprises a diode-connected transistor or a Schottky diode.

20. The apparatus of claim 15, wherein the first device and the second device are each electrically coupled to an inverter circuit or a driver circuit.