Semiconductor device including a gate trench and a source trench

• US 10,636,883 B2
• Filed: 02/20/2019
• Issued: 04/28/2020
• Est. Priority Date: 04/04/2013
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Blank, Oliver
• Primary Examiner(s): Page, Dale E
• Assistant Examiner(s): Jefferson, Quovaunda
• Application Number:
  US16/280,242
• Publication Number:
  US 20190181233A1
• Time in Patent Office: 433 Days
• CPC Class Codes: H01L 21/2255 the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method of forming a semiconductor device includes forming a source trench extending into a semiconductor body from a first surface of the semiconductor body, forming a source trench dielectric and a source trench electrode in the source trench, forming a gate trench dielectric and a gate trench electrode in a gate trench extending into the semiconductor body from the first surface, forming a body region of a first conductivity type between the gate and source trenches, forming a source region of a second conductivity type different from the first conductivity type between the gate and source trenches, forming an interconnection electrically coupling the body region and the source trench electrode, wherein the interconnection adjoins a lateral face of the source trench electrode of the body region, and forming a source contact on the source trench electrode at the first surface.

Claims

1. A method of manufacturing a semiconductor device, the method comprising:

forming a source trench extending into a semiconductor body from a first surface of the semiconductor body;

forming a source trench dielectric and a source trench electrode in the source trench;

forming a gate trench dielectric and a gate trench electrode in a gate trench extending into the semiconductor body from the first surface;

forming a body region of a first conductivity type between the gate and source trenches;

forming a source region of a second conductivity type different from the first conductivity type between the gate and source trenches;

forming an interconnection electrically coupling the body region and the source trench electrode, wherein the interconnection adjoins a lateral face of the source trench electrode of the body region; and

forming a source contact on the source trench electrode at the first surface,

wherein forming the source trench, the source trench dielectric and the source trench electrode comprises;

forming a first source trench and a second source trench;

forming a first insulating layer lining sidewalls and a bottom side of the first and second source trenches;

forming a first conducting material in the first and second source trenches, and wherein the method further comprises;

forming a first recess in the semiconductor body between the first and second source trenches;

forming a second insulating layer lining sidewalls and a bottom side of the first recess; and

filling the first recess with a dummy material configured to be selectively removed with respect to the second insulating layer.

2. The method of claim 1, wherein the recess is filled with at least one of carbon and nitride.

3. The method of claim 1, further comprising removing the second insulating layer selectively with respect to the dummy material at least up to a bottom side of the first recess.

4. The method of claim 3, further comprising:

forming a mask on the first surface, wherein the mask covers only a first part of each of the source trench dielectrics, the first part being arranged between a second part of each of the source trench dielectrics and a respective source trench electrode; and

selectively removing the first part of each of the source trench dielectrics at least up to a bottom side of the first recess.

5. The method of claim 3, further comprising:

removing the second insulating layer from each of the source trench dielectrics selectively with respect to the dummy material at least up to a bottom side of the first recess.

6. The method of claim 3, further comprising:

forming a semiconductor layer on an exposed surface of the semiconductor body between the gate trench and the first and second source trenches.

7. The method of claim 6, wherein the semiconductor layer is formed by selective epitaxial growth.

8. The method of claim 6, wherein forming the body region comprises in-situ doping of the semiconductor layer.

9. The method of claim 6, further comprising:

forming a recess between the semiconductor layer and each of the source trench electrodes; and

forming the interconnection by filling a conducting material in the recess.

10. The method of claim 1, wherein the interconnection is formed to laterally extend through the source trench dielectric in a direction that is parallel to the first surface and is formed to adjoin a lateral face of the source trench electrode and of the body region, the lateral face of the source trench electrode and of the body region being perpendicular to the first surface.

11. The method of claim 10, wherein the source trench and the source trench dielectric are formed such that an interface between the source trench dielectric and the semiconductor body at a sidewall of the source trench is step shaped at a transition between lower and upper parts of the source trench dielectric, and wherein the step shaped interface between the source trench dielectric and the semiconductor body directly contacts the source trench dielectric and the semiconductor body.

12. A method of manufacturing a semiconductor device, the method comprising:

forming a source trench extending into a semiconductor body from a first surface of the semiconductor body;

forming a source trench dielectric and a source trench electrode in the source trench;

forming a gate trench dielectric and a gate trench electrode in a gate trench extending into the semiconductor body from the first surface;

forming a body region of a first conductivity type between the gate and source trenches;

forming a source region of a second conductivity type different from the first conductivity type between the gate and source trenches;

forming an interconnection electrically coupling the body region and the source trench electrode, wherein the interconnection adjoins a lateral face of the source trench electrode of the body region; and

forming a source contact on the source trench electrode at the first surface,

wherein the interconnection is formed to laterally extend through the source trench dielectric in a direction that is parallel to the first surface and is formed to adjoin a lateral face of the source trench electrode and of the body region, the lateral face of the source trench electrode and of the body region being perpendicular to the first surface.

13. The method of claim 12, wherein the source trench and the source trench dielectric are formed such that an interface between the source trench dielectric and the semiconductor body at a sidewall of the source trench is step shaped at a transition between lower and upper parts of the source trench dielectric, and wherein the step shaped interface between the source trench dielectric and the semiconductor body directly contacts the source trench dielectric and the semiconductor body.