Gain compensation for an open loop programmable amplifier for high speed applications

• US 10,637,422 B1
• Filed: 10/31/2018
• Issued: 04/28/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Delshadpour, Siamak, Geng, Xueyang
• Primary Examiner(s): Nguyen, Patricia T
• Application Number:
  US16/176,424
• Publication Number:
  US 20200136579A1
• Time in Patent Office: 545 Days
• CPC Class Codes: H03G 1/0029 using FETs
• CPC Class Codes: H03G 1/0088 using discontinuously variable devices, e.g. switch-operated
• CPC Class Codes: H03G 3/001 Digital control of analog signals
• CPC Class Codes: H03G 3/30 in amplifiers having semiconductor devices

Abstract

Various embodiments relate to a method and apparatus for maintaining constant gain in an open loop gain stage amplifier, the circuit including a reference signal generator configured to generate a plurality of reference voltages, a gain compensation circuit, including a reference selector configured to select one of the plurality of reference voltages for each of a plurality of gain stages, an error amplifier configured to output a control voltage signal to a selector, a selector configured to select which of a plurality of degeneration resistors in the open loop gain stage amplifier to apply the control voltage signal wherein the voltage signal is applied to the gate of at least one of the plurality of degeneration resistors in the open loop gain stage amplifier.

Claims

1. A circuit for maintaining constant gain in an open loop gain stage amplifier, the circuit comprising:

a reference signal generator configured to generate a plurality of reference voltages;

a gain compensation circuit, including;

a reference selector configured to select one of the plurality of reference voltages for each of a plurality of gain stages;

an error amplifier configured to output a control voltage signal to a selector, where the control voltage signal keeps gain constant over process/voltage/temperature (PVT) and adjusts a bias current of a differential pair of transistors;

a selector configured to select which of a plurality of degeneration resistors in the open loop gain stage amplifier to apply the control voltage signal, wherein the control voltage signal is applied to a gate of at least one of the plurality of degeneration resistors in the open loop gain stage amplifier.

2. The circuit for maintaining constant gain in the open loop gain stage amplifier of claim 1, further comprising:

a feedback loop configured to maintain the gain for each of the plurality of gain stages with the plurality of reference voltages.

3. The circuit for maintaining constant gain in the open loop gain stage amplifier of claim 1, wherein the open loop gain stage amplifier is implemented in a complementary metal-oxide semiconductor (“

CMOS”

) transistor and a bipolar CMOS transistor.

4. The circuit for maintaining constant gain in the open loop gain stage amplifier of claim 1, wherein the reference signal generator matches each of the plurality of reference voltages to another one of the plurality of reference voltages.

5. The circuit for maintaining constant gain in the open loop gain stage amplifier of claim 1, wherein the reference signal generator includes a scaling factor to lower current and increase a degeneration resistor value to save current.

6. The circuit for maintaining constant gain in the open loop gain stage amplifier of claim 1, wherein the gain for each of the plurality of gain stages is a ratio of the plurality of reference voltages.

7. A method for maintaining constant gain in an open loop gain stage amplifier, the method comprising the steps of:

generating, by a reference signal generator, a plurality of reference voltages;

selecting, by a reference selector in a gain compensation circuit, one of the plurality of reference voltages for each of a plurality of gain stages;

outputting, by an error amplifier, a control voltage signal to a selector, where the control voltage signal keeps gain constant over process/voltage/temperature (PVT) and adjusts a bias current of a differential pair of transistors;

selecting, by a selector, which of a plurality of degeneration resistors in the open loop gain stage amplifier to apply the control voltage signal, wherein the control voltage signal is applied to a gate of at least one of the plurality of degeneration resistors in the open loop gain stage amplifier.

8. The method for maintaining constant gain in the open loop gain stage amplifier of claim 7, the method further comprising:

maintaining, by a feedback loop, the gain for each of the plurality of gain stages with the plurality of reference voltages.

9. The method for maintaining constant gain in the open loop gain stage amplifier of claim 7, wherein the open loop gain stage amplifier is implemented in a complementary metal-oxide semiconductor (“

CMOS”

) transistor and a bipolar CMOS transistor.

10. The method for maintaining constant gain in the open loop gain stage amplifier of claim 7, wherein the reference signal generator matches each of the plurality of reference voltages to another one of the plurality of reference voltages.

11. The method for maintaining constant gain in the open loop gain stage amplifier of claim 7, wherein the reference signal generator includes a scaling factor to lower current and increase a degeneration resistor value to save current.

12. The method for maintaining constant gain in the open loop gain stage amplifier of claim 7, wherein the gain for each of the plurality of gain stages is a ratio of the plurality of reference voltages.