Alignment testing for tiered semiconductor structure

• US 10,641,819 B2
• Filed: 09/10/2018
• Issued: 05/05/2020
• Est. Priority Date: 10/25/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wang, Mill-Jer, Peng, Ching-Nen, Lin, Hung-Chih, Chen, Hao, Lee, Mincent
• Primary Examiner(s): Assouad, Patrick
• Assistant Examiner(s): Curtis, Sean
• Application Number:
  US16/126,458
• Publication Number:
  US 20190025368A1
• Time in Patent Office: 603 Days
• Field of Search: 3247503, 324765, 324605, 324713, 324769
• CPC Class Codes: G01B 2210/56 Measuring geometric parameters of semiconductor structures, e.g. profile, critical dimensions or trench depth
• CPC Class Codes: G01B 7/12 for measuring diameters
• CPC Class Codes: G01R 31/2601 Apparatus or methods therefor G01R31/2607, G01R31/2642 take precedence
• CPC Class Codes: G01R 31/2834 Automated test systems [ATE]; using microprocessors or computers G01R31/317 takes precedence; ATE for detection of defective computer hardware G06F11/2736
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/2891 related to sensing or controlling of force, position, temperature G01R31/2874 takes precedence; sensing of force G01L; sensing of position G01B, G01D; sensing of temperature G01K; controlling in general G05
• CPC Class Codes: G01R 31/318513 Test of Multi-Chip-Moduls
• CPC Class Codes: G01R 31/54 Testing for continuity
• CPC Class Codes: G01R 31/66 Testing of connections, e.g. of plugs or non-disconnectable joints testing for incorrect line connections G01R31/55

Abstract

Among other things, one or more techniques or systems for evaluating a tiered semiconductor structure, such as a stacked CMOS structure, for misalignment are provided. In an embodiment, a connectivity test is performed on vias between a first layer and a second layer to determine a via diameter and a via offset that are used to evaluate misalignment. In an embodiment, a connectivity test for vias within a first layer is performed to determine an alignment rotation based upon which vias are connected through a conductive arc within a second layer or which vias are connected to a conductive pattern out of a set of conductive patterns. In this way, the via diameter, the via offset, or the alignment rotation are used to evaluate the tiered semiconductor structure, such as during a stacked CMOS process, for misalignment.

Claims

1. A method for evaluating a tiered semiconductor structure, comprising:

evaluating connectivity between a first set of vias within a first layer of a tiered semiconductor structure and spaced apart by a first pitch and a second set of vias within a second layer of the tiered semiconductor structure and spaced apart by a second pitch different than the first pitch;

determining a first offset based upon an offset measurement between a target design via and a measured center via, the first offset comprising;

an offset distance determined based upon a number of vias between the target design via and the measured center via and a pitch difference between the first pitch and the second pitch; and

evaluating the tiered semiconductor structure for misalignment based upon the first offset.

2. The method of claim 1, wherein the first offset comprises an offset direction.

3. The method of claim 1, comprising:

determining a via diameter for vias of the first set of vias, wherein the evaluating the tiered semiconductor structure for misalignment comprises;

evaluating the tiered semiconductor structure for misalignment based upon the via diameter.

4. The method of claim 1, wherein:

the measured center via corresponds to a middle via of a row of vias within the first set of vias that contact vias within the second set of vias, and

the target design via corresponds to an intended center via of a row of vias within the first set of vias that are designed to contact vias within the second set of vias.

5. The method of claim 1, comprising:

evaluating connectivity, through a conductive arc within a third layer of the tiered semiconductor structure, between a first via, a second via, and a third via of a fourth layer of the tiered semiconductor structure to determine an alignment rotation.

6. The method of claim 5, wherein:

the third layer is different than the first layer and the second layer, and

the fourth layer is different than the first layer and the second layer.

7. The method of claim 5, wherein the evaluating connectivity, through a conductive arc within a third layer of the tiered semiconductor structure comprises:

transmitting a first test signal through the first via and measuring a response at the second via and the third via to yield first results, and

transmitting a second test signal through the second via and measuring a response at the first via and the third via to yield second results.

8. The method of claim 5, comprising:

evaluating the tiered semiconductor structure for misalignment based upon the alignment rotation.

9. The method of claim 1, comprising:

identifying the measured center via based upon the evaluating connectivity.

10. The method of claim 1, wherein the evaluating the tiered semiconductor structure for misalignment comprises:

evaluating the tiered semiconductor structure for misalignment during a CMOS stacking process of one or more tiers of the tiered semiconductor structure.

11. The method of claim 1, comprising:

transmitting a testing signal to perform a connectivity test, during which the evaluating connectivity is performed, utilizing at least one of a contact probe, a contactless coupling, or a probe coupling hybrid.

12. The method of claim 11, wherein the transmitting comprises:

transmitting the testing signal utilizing at least one of;

a direct testing signal from automatic test equipment (ATE);

or

a testing trigger created by a built in self testing engine (BIST) employed by the ATE.

13. A method for evaluating a tiered semiconductor structure, comprising:

evaluating connectivity between a first set of vias within a first layer of a tiered semiconductor structure and spaced apart by a first pitch and a second set of vias within a second layer of the tiered semiconductor structure and spaced apart by a second pitch different than the first pitch;

identifying a measured center via based upon the evaluating;

determining an offset based upon a number of vias between a target design via and the measured center via; and

evaluating the tiered semiconductor structure for misalignment based upon the offset.

14. The method of claim 13, wherein the determining comprises:

determining the offset based upon a pitch difference between the first pitch and the second pitch.

15. The method of claim 13, comprising:

invoking at least one of a testing unit, a repair unit, or a fault tolerance unit to process one or more tiers during stacked CMOS production processing of the tiered semiconductor structure.

16. The method of claim 13, wherein the evaluating connectivity comprises:

determining a via connection count corresponding to a number of via connections that pass a connectivity test.

17. The method of claim 16, comprising:

determining a via diameter based upon the via connection count and based upon a pitch difference between the first pitch and the second pitch, wherein the evaluating the tiered semiconductor structure for misalignment comprises;

evaluating the tiered semiconductor structure for misalignment based upon the via diameter.

18. A method for evaluating a tiered semiconductor structure, comprising:

evaluating connectivity between a first set of vias within a first layer of a tiered semiconductor structure and spaced apart by a first pitch and a second set of vias within a second layer of the tiered semiconductor structure and spaced apart by a second pitch different than the first pitch to determine a via connection count corresponding to a number of vias within the first set of vias that contact vias within the second set of vias;

identifying a measured center via based upon the via connection count;

determining an offset based upon a number of vias between a target design via and the measured center via and based upon a pitch difference between the first pitch and the second pitch; and

evaluating the tiered semiconductor structure for misalignment based upon a via diameter for vias of the first set of vias and the offset.

19. The method of claim 18, comprising:

determining the via diameter for vias of the first set of vias based upon the via connection count.

20. The method of claim 18, wherein the via diameter is based upon the pitch difference.