Critical path architect
First Claim
1. A system, comprising:
- a processor; and
memory having stored thereon instructions that, when executed by the processor, cause the processor to;
analyze timing data of an integrated circuit, wherein the timing data includes transition times for cells along paths of the integrated circuit;
identify instances of timing degradation for the cells along the paths of the integrated circuit in which the output transition time is different than the input transition time;
recommend changes for the instances of the cells along the paths having timing degradation such that the output transition time is substantially similar to the input transition time; and
generate a data file to build an integrated circuit based on the recommended changes.
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Abstract
Various implementations described herein are directed to a system and methods for implementing a critical path architect. In one implementation, the critical path architect may be implemented with a system having a processor and memory including instructions stored thereon that, when executed by the processor, cause the processor to analyze timing data of an integrated circuit. The timing data may include transition times for cells along paths of the integrated circuit. The instructions may cause the processor to identify instances of timing degradation for the cells along the paths of the integrated circuit. The instructions may cause the processor to recommend changes for the instances of the cells along the paths having timing degradation.
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Citations
22 Claims
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1. A system, comprising:
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a processor; and memory having stored thereon instructions that, when executed by the processor, cause the processor to; analyze timing data of an integrated circuit, wherein the timing data includes transition times for cells along paths of the integrated circuit; identify instances of timing degradation for the cells along the paths of the integrated circuit in which the output transition time is different than the input transition time; recommend changes for the instances of the cells along the paths having timing degradation such that the output transition time is substantially similar to the input transition time; and generate a data file to build an integrated circuit based on the recommended changes. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A non-transitory computer readable storage medium, the non-transitory computer readable storage medium having stored thereon instructions that, when executed by a processor, cause the processor to:
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analyze timing data of an integrated circuit, wherein the timing data includes input and output transition times for cells along paths of the integrated circuit; identify instances of the cells along the paths of the integrated circuit in which an output transition time is different than an input transition time; recommend changes for the instances of the cells along the paths having the output transition time different than the input transition time such that the output transition time is substantially similar to the input transition time; and generate a data file to build an integrated circuit based on the recommended changes. - View Dependent Claims (15, 16, 17, 18, 19)
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20. A method, comprising:
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analyzing timing data of an integrated circuit, wherein the timing data includes an input transition time and an output transition time for cells along paths of the integrated circuit; identifying instances of the cells along the paths of the integrated circuit in which the output transition time is different than the input transition time; recommending changes for the instances of the cells along the paths such that the output transition time is substantially similar to the input transition time, wherein recommending changes includes one or more of; upsizing the instances of the cells along the paths, modifying a threshold voltage of the instances of the cells along the paths, increasing a width of a wire trace along the paths of the integrated circuit that cause timing degradation, increasing spacing between wire traces along the paths of the integrated circuit that cause timing degradation, and debanking or unbanking multi-bit flip-flops into individual flip-flops; and generating a data file to build an integrated circuit based on the recommended changes. - View Dependent Claims (21, 22)
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Specification