Method and apparatus for built-in self-test of CDR and non-CDR components with an on substrate test signal generator

• US 10,641,823 B2
• Filed: 03/17/2017
• Issued: 05/05/2020
• Est. Priority Date: 03/17/2017
• Status: Active Grant

• Current Assignee: PhotonIC Technologies (Shanghai) Co., Ltd.
• Original Assignee: PhotonIC Technologies (Shanghai) Co., Ltd.
• Inventors: Lu, Ming, Chiang, Patrick Yin, Ma, Jianxu, Bai, Rui, Chen, Xuefeng, Wang, Juncheng
• Primary Examiner(s): Nguyen, Vinh P
• Application Number:
  US15/773,304
• Publication Number:
  US 20200003830A1
• Time in Patent Office: 1,145 Days
• CPC Class Codes: G01R 31/2856 Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence

Abstract

An apparatus comprises one or more non-clock and data recovery (CDR) components on a substrate, a signal generator on the substrate and coupled to at least one of the one or more non-CDR components, and a CDR component on the substrate and coupled to the one or more non-CDR components, wherein the CDR component is configured to recover clock data from a received signal by the CDR component, and configured to determine a signal based on the received signal and the clock data.

Claims

1. An apparatus comprising:

one or more non-clock and data recovery (CDR) components comprising one or more amplifiers on a substrate;

a signal generator on the substrate and configured to provide a test signal for testing one or more components selected from a group consisting of the one or more non-CDR components and a CDR component on the substrate; and

the CDR component on the substrate and coupled to the one or more non-CDR components, wherein the CDR component is;

configured to recover clock data from an electrical signal received by the the one or more non-CDR components, and

configured to generate a recovered data signal based on the electrical signal and the clock data.

2. The apparatus of claim 1, wherein the one or more amplifiers comprise a trans-impedance amplifier or a limiting amplifier.

3. The apparatus of claim 1, further comprising a signal checker on the substrate and coupled to the CDR component or at least one of the one or more non-CDR components, wherein the signal checker is configured to determine a measure upon receipt of the test signal after the test signal passes through the one or more components selected from the group consisting of the one or more non-CDR components and the CDR component.

4. The apparatus of claim 1, further comprising a signal adjuster on the substrate and coupled to the signal generator, wherein the signal adjuster is configured to adjust one or more parameters of the test signal.

5. The apparatus of claim 4, wherein the one or more parameters of the test signal are selected from a group consisting of amplitude, bandwidth, jitter, and noise level.

6. The apparatus of claim 5, wherein the signal adjuster comprises an amplifier coupled to a tunable current source, and wherein the amplifier and the tunable current source are collectively configured to adjust amplitude of the test signal, gain of the amplifier being adjustable through tuning the tunable current source.

7. The apparatus of claim 5, wherein the signal adjuster comprises a tunable resistor or a tunable capacitor, and wherein the tunable resistor or the tunable capacitor is configured to adjust the bandwidth of the test signal.

8. The apparatus of claim 5, wherein the signal adjuster comprises a delay line coupled to a tunable radio-frequency (RF) source, and wherein the delay line and the tunable RF source are collectively configured to adjust the jitter of the test signal.

9. The apparatus of claim 8, wherein the tunable RF source is configured to provide sinusoidal RF signals with tunable frequency or tunable power.

10. The apparatus of claim 5, wherein the signal adjuster comprises a tunable noise source configured to adjust noise level applied to the test signal.

11. The apparatus of claim 4, further comprising a programmable switch coupled to the signal adjuster and at least two components selected from a group consisting of the CDR component and the one or more non-CDR components.

12. The apparatus of claim 11, wherein the programmable switch is configured to selectively direct the test signal to a component selected from a group consisting of the one or more non-CDR components and the CDR component.