Method and system for detecting and isolating intermittence in multi-circuit connectivity elements

• US 10,641,826 B2
• Filed: 02/20/2018
• Issued: 05/05/2020
• Est. Priority Date: 02/20/2018
• Status: Active Grant

• Current Assignee: Universal Synaptics Corp.
• Original Assignee: Universal Synaptics Corp.
• Inventors: Kelly, Patrick, Kelly, Jayson, Sorensen, Brent, Sorensen, Paul
• Primary Examiner(s): Assouad, Patrick
• Assistant Examiner(s): Zhang, Haidong
• Application Number:
  US15/900,133
• Publication Number:
  US 20190257882A1
• Time in Patent Office: 805 Days
• CPC Class Codes: G01R 31/318566 Comparators; Diagnosing the device under test
• CPC Class Codes: G05B 19/0428 Safety, monitoring G05B19/0423 takes precedence
• CPC Class Codes: G05B 23/0262 Confirmation of fault detection, e.g. extra checks to confirm that a failure has indeed occurred
• CPC Class Codes: G06F 11/2215 to test error correction or detection circuits
• CPC Class Codes: G06F 11/24 Marginal checking or other specified testing methods not covered by G06F11/26, e.g. race tests

Abstract

Embodiments are directed to identifying intermittent faults in a unit under test (UUT), and to mapping interconnections between connection points in a UUT. In one scenario, a testing apparatus includes an interface for electrically attaching the UUT to a testing module and an input circuit for supplying an individual stimulus signal to each unpowered connection point in the UUT. The testing apparatus also includes an active intermittence detecting circuit electronically connected to each connecting point in the UUT. A stimulus signal is applied simultaneously to each connecting line, so that an intermittent fault on any line will generate a trigger on those connection lines that have an intermittent fault. The testing apparatus also includes a logic circuit that determines when a trigger has been generated on the UUT, determines the connection point of the trigger, assigns a timestamp to the intermittent fault, and generates reporting data for the intermittent fault.

Claims

1. A testing apparatus for identifying transient connection conditions constituting intermittent faults on connecting paths within a unit under test (UUT), the testing apparatus comprising:

a set of one or more testing modules, each testing module comprising;

a set of stimulus circuits that are individually controllable as a source or sink of stimulus signals and are individually electrically connectable to one or more connection points in the UUT; and

a set of intermittence-detecting circuits that are individually electrically connectable to each of the one or more connection points in the UUT;

a logic circuit configured to perform the following;

determine when a transient event has occurred at any one of the set of intermittence-detecting circuits to thereby trigger the testing apparatus;

determine the one or more connection points within the UUT that triggered the testing apparatus to thereby identify an intermittent fault;

assign a timestamp to each identified intermittent fault; and

generate a set of data defining each intermittent fault for reporting to a testing apparatus controller; and

an interface for electrically attaching at least one UUT to one or more of the set of testing modules, each UUT comprising a plurality of connection lines configured to connect electronic components.

2. The testing apparatus of claim 1, wherein the set of stimulus circuits are configured to return paths for the stimulus signals.

3. The testing apparatus of claim 1, wherein reference signals of the intermittence-detecting circuits are self-calibrating as commanded by the testing apparatus controller.

4. The testing apparatus of claim 1, wherein the logic circuit is further configured to characterize the amplitude and/or duration of each identified intermittent fault.

5. The testing apparatus of claim 4, wherein the amplitude and/or duration of each identified intermittent fault is reported to the testing apparatus controller as part of the set of data for each intermittent fault.

6. The testing apparatus of claim 1, wherein each intermittence-detecting circuit is configured to handle at least a specified range of input transient magnitudes, both in amplitude and duration.

7. The testing apparatus of claim 6, wherein each intermittence-detecting circuit is configured to compensate for any quiescent voltage generated by the stimulus signals on the UUT.

8. The testing apparatus of claim 1, wherein determining the one or more connection points within the UUT causing the trigger comprises identifying a coordinate-based location of the trigger generated by a faulting circuit.

9. The testing apparatus of claim 1, wherein the testing apparatus is implemented solely in hardware and/or firmware.

10. The testing apparatus of claim 1, wherein the set of one or more testing modules are stackable to accommodate a plurality of connection test points.

11. The testing apparatus of claim 1, wherein the intermittence-detecting circuits are electrically connected to every connection line or connection point of the UUT for the full duration of the test.

12. A method of mapping interconnections between connection points in a unit under test (UUT), the method comprising:

accessing a test module comprising at least one UUT, the UUT comprising one or more connection points;

instantiating a database table with one or more database table entries configured to list connections identified between the connection points, wherein the database table entries are configured to store a resistance level measured at each connection point;

provisioning a switch connected to each connection point to automatically detect interconnections on the UUT, the switches being configured to identify which connection points in the circuit board are electrically connected; and

storing an indication of the identified interconnections in the database table entries, such that the UUT'"'"'s interconnections are mapped and stored in the database table.

13. The method of claim 12, further comprising storing the measured and recorded resistance level for each connection point of a known good UUT in the data storage system.

14. The method of claim 12, further comprising identifying which pin(s) on the UUT will provide a return path for each of the identified interconnections.

15. The method of claim 12, wherein the interconnections of the UUT are detected without knowledge of the actual internal connections of the UUT that is being tested.

16. The method of claim 12, wherein the interconnections of the UUT are detected without implementing software programming steps that are specific to the UUT that is being tested.

17. A method, performed at a computer system including at least one processor and a memory, for detecting intermittent faults in a system, the method comprising:

electrically attaching at least one unit under test (UUT) to one or more testing modules, each UUT comprising a plurality of connection lines configured to connect electronic components;

supplying a stimulus signal to one or more connection lines in the UUT;

initializing a self-calibration cycle of a reference signal, such that the reference signal calibrates itself to a quiescent input level;

determining when a trigger has been generated on the UUT, the generated trigger identifying an intermittent fault;

determining the location of the trigger on the UUT, the trigger location identifying a faulting circuit that has the intermittent fault;

reporting a timestamp of the faulting circuit event along with one or more portions of associated data related to the intermittent fault; and

displaying the faulting circuit on a graphic display of the UUT, allowing an operator to view the fault and repair it.

18. The method of claim 17, further comprising reporting one or more portions of associated data related to the detected intermittent fault along with the reported timestamp.

19. The method of claim 17, wherein an active intermittence detection circuit is on every connection line of the UUT for the full duration of the test.

20. The method of claim 19, wherein each connection line of the system is monitored simultaneously by control logic in the system.