Smooth waveguide structures and manufacturing methods
1. An integrated optical structure comprising:
- a semiconductor-on-insulator substrate comprising a semiconductor device layer;
a wire waveguide formed in the semiconductor device layer, the wire waveguide having a top surface and sidewalls and comprising a tapered region decreasing in width towards a narrow end; and
a second waveguide disposed above or below the tapered region of the wire waveguide at the narrow end, the second waveguide made from a different material than the wire waveguide, and the second waveguide and wire waveguide together forming an optical mode converter,wherein the sidewalls, along a length of the wire waveguide in the tapered region, do not extend laterally beyond the top surface of the wire waveguide and substantially consist of sidewall portions coinciding with crystallographic planes of the wire waveguide, andwherein, along a portion of the tapered region of the wire waveguide that has a width of less than 0.5 μ
m, a return loss is less than −
40 dB/mm across an operating wavelength range.
In integrated optical structures (e.g., silicon-to-silicon-nitride mode converters) implemented in semiconductor-on-insulator substrates, wire waveguides whose sidewalls substantially consist of portions coinciding with crystallographic planes and do not extend laterally beyond the top surface of the wire waveguide may provide benefits in performance and/or manufacturing needs. Such wire waveguides may be manufactured, e.g., using a dry-etch of the semiconductor device layer down to the insulator layer to form a wire waveguide with exposed sidewalls, followed by a smoothing crystallographic wet etch.
|LOW-COST PASSIVE OPTICAL WAVEGUIDE USING SI SUBSTRATE|
Patent #US 20120138568A1
Current AssigneeIntel Corporation
Sponsoring EntityIntel Corporation
|Semiconductor device having embedded strain-inducing pattern and method of forming the same|
Patent #US 8,884,298 B2
Current AssigneeSamsung Electronics Co. Ltd.
Sponsoring EntitySamsung Electronics Co. Ltd.
- 1. An integrated optical structure comprising:
a semiconductor-on-insulator substrate comprising a semiconductor device layer; a wire waveguide formed in the semiconductor device layer, the wire waveguide having a top surface and sidewalls and comprising a tapered region decreasing in width towards a narrow end; and a second waveguide disposed above or below the tapered region of the wire waveguide at the narrow end, the second waveguide made from a different material than the wire waveguide, and the second waveguide and wire waveguide together forming an optical mode converter, wherein the sidewalls, along a length of the wire waveguide in the tapered region, do not extend laterally beyond the top surface of the wire waveguide and substantially consist of sidewall portions coinciding with crystallographic planes of the wire waveguide, and wherein, along a portion of the tapered region of the wire waveguide that has a width of less than 0.5 μ
m, a return loss is less than −
40 dB/mm across an operating wavelength range.
- View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
- 9. A photonic integrated circuit (PIC) comprising:
an optical mode converter comprising a first waveguide made of a first material and tapered towards one end, and disposed above or below the first waveguide at the tapered end, a second waveguide made of a second material, a refractive index of the first material being greater than a refractive index of the second material, wherein the first waveguide is a wire waveguide having a top surface and sidewalls, and wherein the sidewalls, along at least a portion of a length of the wire waveguide at the tapered end, do not extend laterally beyond the top surface and substantially consist of sidewall portions coinciding with crystallographic planes of the wire waveguide.
- View Dependent Claims (10, 11, 12, 13)
This disclosure relates to integrated optical structures and methods for manufacturing them. Some embodiments concern, in particular, optical mode converters.
Many photonic integrated circuits (PICs) include mode converters that transfer light between different device layers from one waveguide to another. For example, PICs otherwise implemented in silicon may utilize, at the input(s) and/or output(s) of the PIC, silicon-nitride-based grating couplers because they can operate across a wider temperature range than silicon-based couplers. In this case, the mode converter serves to couple light from a silicon waveguide in the silicon device layer into a silicon-nitride waveguide disposed above the silicon waveguide and coupled to the silicon-nitride grating coupler (or vice versa). In the coupling region, the silicon waveguide is tapered down to a small cross section. Over a large portion of the taper, light is therefore highly confined to a small cross-sectional area, which makes the light more sensitive to any surface roughness. The relatively high surface roughness achieved with conventional manufacturing techniques tends to result in a correspondingly high scattering loss from this portion of the taper. The high scattering loss, in turn, contributes to a higher insertion loss for the device, and the backscattered portion of the scattered light contributes to a higher return loss.
Disclosed herein are semiconductor structures and manufacturing methods that result in waveguides with smooth sidewalls for use, e.g., in low-loss mode converters. In accordance with various embodiments, a semiconductor wire waveguide created by etching the semiconductor device layer of a semiconductor-on-insulator substrate (e.g., the silicon device layer of a silicon-on-insulator (SOI) substrate) down to the insulator (e.g., silicon oxide) layer is smoothed by an additional crystallographic etch, resulting in smooth sidewall portions coinciding with the crystallographic planes of the wire waveguide. The crystallographic smoothing etch may be pinned between the insulator layer of the substrate and an etch mask layer disposed on top of the semiconductor device layer, forming a cross-sectionally triangular undercut into the wire waveguide, with sidewall portions extending inward from the edges of the top and bottom surfaces of the waveguide to meet at a medial horizontal plane. In the corresponding cross section of the wire waveguide, which roughly resembles an “hourglass” in shape, the minimum width (corresponding to the “waist” at the medial plane) is smaller than the width at the top surface (herein also the “defined width”) of the wire waveguide, which is the width defined via photolithographic patterning of the etch mask used in the wire-waveguide forming etch. Beneficially, this shape reduces the cross-sectional area of the waveguide, compared with a waveguide of the same defined width that has substantially straight vertical sidewalls (wherein “substantially” allows for small manufacturing deviations from perfectly vertical sidewalls, e.g., with angles of up to 5°), allowing smaller cross sections to be achieved without the need for smaller patterned features.
Since any given semiconductor manufacturing process (also often referred to as a “process node” or “technology node”) is limited by the smallest patternable feature it can achieve, and since manufacturing costs generally increase significantly with smaller feature sizes, the ability to reduce the cross section of the waveguide without reducing the defined width can entail cost savings in applications where a small waveguide cross section is desirable. Such applications include, for example, mode converters, where a small cross section of the wire waveguide (e.g., made of silicon) may serve to match the effective index of the wire waveguide with that of a second waveguide made from a material with lower refractive index (such as, e.g., silicon nitride). Importantly, achieving small waveguide cross sections simultaneously with smooth waveguide sidewalls improves device performance due to reduced scattering losses and improved phase coherence. Applications that rely on good phase coherence include, e.g., finite impulse response (FIR) filters, which include two or more waveguides with fixed and deterministic phase offsets therebetween.
In one aspect, the present disclosure provides an integrated optical structure including a semiconductor-on-insulator substrate comprising a semiconductor device layer and a wire waveguide formed in the semiconductor device layer. The wire waveguide may be tapered in width. The wire waveguide has a top surface and sidewalls, and, along at least a portion of its length, the sidewalls do not extend laterally (meaning, along a direction defined by the intersection of the waveguide cross section with the plane of the substrate) beyond the top surface (corresponding to the defined width) of the wire waveguide and substantially consist of sidewall portions coinciding with crystallographic planes of the wire waveguide. (In this context, the term “substantially” allows for small transitional areas between the sidewall portions or between a sidewall portion and the top or bottom surface of the waveguide that do not necessarily coincide with the crystallographic planes. Such transitional areas, if present at all, amount to only a small fraction of the overall sidewall area, e.g., less than 1%.) The sidewall portions may include, along at least the portion of the length of the wire waveguide, one or more planar upper portions extending from a top edge of the wire waveguide at an acute angle (that is, an angle smaller than 90°) with respect to the top surface of the wire waveguide and one or more planar lower portions extending from a bottom edge of the wire waveguide at an acute angle with respect to a bottom surface of the wire waveguide, the upper and lower portions meeting at a medial horizontal plane of the wire waveguide. Multiple planar upper and lower portions may occur along the length of the waveguide, e.g., as a result of waveguide tapering in width. The individual sidewall portions coinciding with crystallographic planes may each be atomically smooth. The surface roughness the waveguide walls (e.g., measured in terms of the root mean square roughness, which is the standard deviation of the surface position) may be sub-nanometer, rendering the sidewalls optically smooth at standard operating wavelengths (which are on the order of a micrometer). In one embodiment, the wire waveguide has, along a portion of the waveguide having a width of less than 0.5 μm, return losses less than −40 dB/mm across an operating wavelength range (e.g., the range from 1200 nm to 1400 nm).
The integrated optical structure may further include a rib waveguide formed in the semiconductor device layer on top of and parallel to the wire waveguide, and the rib waveguide may be tapered, in width and/or height, in the same direction along the length (or axis) of the rib waveguide as the wire waveguide. Further, at the narrow end of the tapered wire waveguide, a second waveguide made from a different material may be disposed above or below the wire waveguide (optionally with a cladding layer between the wire waveguide and the second waveguide), the wire waveguide and the second waveguide together forming a waveguide mode converter. In various embodiments, the refractive index of the wire-waveguide material is greater than the refractive index of the material of the second waveguide. For example, the wire waveguide may be made of silicon and the second waveguide of silicon nitride.
In another aspect, a PIC including an optical mode converter may be provided. The optical mode converter may include a first waveguide made of a first material and tapered towards one end, and, disposed above or below the first waveguide at the tapered end, a second waveguide made of a second material, a refractive index of the first material being greater than a refractive index of the second material. The first waveguide is a wire waveguide having a top surface and sidewalls that, along at least a portion of a length of the wire waveguide, do not extend laterally beyond the top surface of the wire waveguide and substantially consist of sidewall portions coinciding with crystallographic planes of the wire waveguide. The wire waveguide may be formed in a silicon device layer of a silicon-on-insulator substrate, and the second waveguide may be formed in a silicon-nitride layer disposed above the silicon device layer (the silicon and silicon-nitride layers optionally being separated by a cladding layer). The PIC may further include a silicon-nitride grating coupler coupled to the second waveguide and one or more silicon devices coupled to the wire waveguide.
In yet another aspect, the present disclosure pertains to a method of manufacturing an integrated optical structure. The method involves creating a wire-waveguide etch mask above a semiconductor device layer of a semiconductor-on-insulator substrate, dry-etching the masked semiconductor device layer down to an insulator layer of the substrate to form a semiconductor wire waveguide with exposed sidewalls, and crystallographically wet-etching the semiconductor wire waveguide to smoothen the exposed sidewalls, the etch being pinned between the insulator layer of the substrate and the wire-waveguide mask. For the crystallographic wet etch, an anisotropic etchant with an etch-rate ratio of at least 20 may be used. The etchant may, for example, include tetramethyl ammonium hydroxide. The method may further include, prior to creating the wire-waveguide etch mask, creating a rib-waveguide etch mask above the semiconductor device layer and partially etching the semiconductor device layer to form a semiconductor rib waveguide, wherein the semiconductor wire waveguide is formed at least in part running underneath the rib waveguide. The rib-waveguide etch mask and the wire-waveguide etch mask may both be tapered so as to result in tapering of the semiconductor rib waveguide and the semiconductor wire waveguide in a common direction. In some embodiments, the semiconductor rib waveguide is tapered vertically down to vanishing. The semiconductor device layer and the semiconductor wire waveguide may be made of silicon, and a silicon-nitride waveguide may further be created above the silicon wire waveguide depositing a silicon nitride layer above the top silicon layer, and patterning and etching the silicon nitride layer.
The foregoing will be more readily understood from the following detailed description of various example embodiments, in particular, when taken in conjunction with the drawings, in which:
The present disclosure relates, in various embodiments, to integrated optical structures implemented on semiconductor-on-insulator substrates, herein understood to be layered substrates that include a semiconductor layer disposed on top of an electrically insulating, dielectric layer, which is, in turn, usually disposed on another semiconductor layer that serves as a mechanical base layer or “handle.” The optical structures are formed at least partially in the top semiconductor layer, which is therefore also referred to as the “semiconductor device layer.” In SOI substrates, the handle and semiconductor device layers are made of silicon, and the insulator layer is often made of silicon dioxide. Alternative semiconductor-on-insulator substrates may use, for instance, germanium, silicon-germanium, or a compound semiconductor such as a III-V material (e.g., gallium arsenide or indium phosphide) for the semiconductor device layer. Additional layers of material or device components, such as a dielectric cladding layer, one or more further semiconductor components, and/or metal contacts for electrical connections may be disposed above the semiconductor device layer. In the absence of a cladding layer, air serves as the cladding. Certain embodiments described herein include silicon waveguides formed in SOI substrates, in some instances in conjunction with silicon nitride waveguides disposed above the silicon waveguides. The principles, structural features, and manufacturing steps discussed herein are, however, generally also applicable to other materials and material combinations, subject to any needs or preferences of a given application. For example, instead of implementing a waveguide in the semiconductor device layer of a semiconductor-on-insulator substrate, semiconductor (e.g., indium phosphide) waveguides as described in the following may be grown with one or more intervening epilayers on a semiconductor (e.g., indium phosphide) substrate; in this case, the epilayer(s), used in lieu of the insulator layer of a semiconductor-on-insulator substrate, serve as the stop layer.
As will be appreciated by those of ordinary skill in the art, changes in width of the wire waveguide 100 along its length (i.e., in a direction perpendicular to the plane of the drawing) cause discontinuities generally resulting in multiple planar upper and lower sidewall portions 114, 120 along the length of the wire waveguide 100. For example, a width taper of the wire waveguide 100, as used in various embodiments, may result from many discontinuities each approximately an atomic layer in thickness. These discontinuities form the boundaries of the individual planar upper and lower sidewall portions 114, 120. In other words, the sidewalls in their entirety do not each coincide with a single crystallographic plane for the upper portion and a single crystallographic plane for the lower portion; however, within each waveguide segment of constant width, the corresponding upper and lower sidewall portions 114, 120 coincide with respective crystallographic planes. The individual side wall portions tend to be atomically smooth due to their coincidence with crystallographic planes, and the residual surface roughness (e.g., the root mean square roughness) along the length of the taper resulting from the discontinuities is on the order of a single atomic layer thickness. Consequently, even in the tapered region, the surface roughness of the sidewalls is much smaller than the natural variation of roughness occurring with standard photolithographic and dry etching processes. In various embodiments, the sidewalls of the wire waveguide 100 have a surface roughness in the sub-nanometer range, which is orders of magnitudes below the wavelength of the guided light (which may be, e.g., 1300 nm or 1550 nm, depending on the application); the sidewalls are, in that sense, optically smooth. Beneficially, not only does the smoothness of the sidewalls provide for low scattering losses, but the sidewalls also do not extend laterally beyond (and, in fact, form a waist smaller than) the defined width of the wire waveguide, which reduces the cross-sectional area.
Silicon and SOI wafers come in different orientations of their macroscopic features (such as their top surface 106 and, if applicable, the “flat” along which a segment of an otherwise circular wafer is cut off) relative to the silicon crystal orientations.
In some embodiments, wire waveguides within a (100) SOI wafer 220 are oriented in the  or [0
Wire waveguides 100, 240, as described above, may find use in various applications. For example, in a mode converter that couples light between waveguides of different materials having different respective indices of refraction (e.g., silicon and silicon nitride), the waveguide with the higher index of refraction may be tapered down in the coupling region to match the effective index of the other waveguide, and in order to achieve a low cross section while avoiding excessive scattering losses at the narrow end of the taper and maintaining good phase coherence, the tapered waveguide may take the shape of a wire waveguide 100, 240 with atomically smooth sidewalls tilted inward to form a waist narrower than the waveguide width. A mode converter may be used as a subcomponent within the delay arm(s) of an FIR filter (e.g., a single-delay filter such as an asymmetric Mach-Zehnder interferometer, or a many-delay filter such as a lattice filter or arrayed waveguide grating (AWG)), allowing the delay(s) to be implemented entirely in silicon nitride (or another material with low temperature sensitivity) to render the filter spectrum temperature-insensitive. The mode converter may, in this case, transfer the light from the silicon-nitride delay section(s) to the temperature-sensitive sections of the waveguide, which may be kept equal in length across interferometer arms such that their temperature dependence does not cause the spectrum to shift with ambient temperature. Alternatively, all interferometer arms may include both silicon sections and silicon nitride sections, whose lengths may differ between the interferometer arms in such a way that the overall temperature sensitivity (accounting for the smaller, but non-zero sensitivity of the silicon nitride) of the filter is further reduced. Similar principles can be applied to waveguides of different polarization sensitivities (using a mode converter to transfer light between them) to make polarization-insensitive filters. Various of these applications a contingent upon good phase coherence.
Outside the realm of mode converters, wire waveguides 100, 240 as described herein may be used, e.g., in bend sections of any device to reduce the footprint of the device. As another example, an interferometric wavelength locker may utilize two waveguides of different widths as the interferometer arms, achieving the different widths by using a rib waveguide in one arm and a wire waveguide 100, 240 in the other arm. Yet another application involves the use of a wire waveguide layer as the grating coupler layer in a PIC.
The mode converter 300 includes a wire waveguide 302, a top waveguide 304, and a rib waveguide 306. Projected into the plane of the wafer 220 (as depicted in
With reference to
The wire waveguide 302 may likewise be tapered (in width), as shown in
In the tapered region of the wire waveguide 302, smooth sidewalls, as described herein (e.g., with respect to
Power coupling between the forward and backward propagating optical modes in a waveguide is generally proportional to the surface variance (i.e., standard deviation squared) (see, e.g., F. Ladouceur and L. Poladian, “Surface roughness and backscattering,” Optics Letters, Vol. 21 No. 22, Nov. 15 (1996)). Further, the smaller the diameter of an optical mode, the more sensitive is the optical mode to surface roughness. In optical mode converters in accordance with various embodiments, where the mode diameter along the waveguide taper may become as small as, e.g., 250 nm, the surface roughness resulting from conventional manufacturing processes tends to cause problematically high return losses. Sidewall smoothing of wire waveguides in accordance herewith can reduce the return losses by about 10 dB in some embodiments. In one embodiment, a mode converter with a wire waveguide having smoothened sidewalls has an overall return loss, accounting for both backscattering along the walls and reflection at the tip of the taper, of less than −30 dB across the operating wavelength range from 1260 nm to 1360 nm. In some embodiments, wire waveguide with widths of less than 0.5 μm (as may be useful to achieve strong mode confinement) can, as a result of sidewall smoothing in accordance herewith, achieve return losses per unit length of waveguide of less than −40 dB/mm.
Referring now to the flow chart of
The starting point 502 of the method 500 is an SOI substrate 600 (shown in
Following creation of the rib waveguide 306, a silicon dioxide cap layer 612 (shown in
Following the creation of the wire waveguide 302 and smoothening of its sidewalls, the PIC may be planarized with a dielectric (e.g., oxide, a polymer, or generally any dielectric material having a refractive index lower than the top waveguide 304) fill (shown in
While the mode converter 300 depicted in
Although embodiments have been described with reference to specific example embodiments, it will be evident that various modifications and changes may be made to these embodiments without departing from the broader scope of the disclosure. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.