Lateral MOSCAP phase adjuster

• US 10,642,077 B1
• Filed: 11/20/2018
• Issued: 05/05/2020
• Est. Priority Date: 11/20/2018
• Status: Active Grant

• Current Assignee: Nokia Solutions and Networks US LLC (Nokia Corporation)
• Original Assignee: Elenion Technologies, LLC (Nokia Corporation)
• Inventors: Andy, Lim Eu-Jin, Ma, Yangjin, Horth, Alexandre, Liu, Yang
• Primary Examiner(s): Kim, Ellen E
• Application Number:
  US16/196,947
• Publication Number:
  US 20200159048A1
• Time in Patent Office: 532 Days
• CPC Class Codes: G02F 1/025 in an optical waveguide structure G02F1/017, G02F1/2257 take precedence
• CPC Class Codes: G02F 2202/104 poly-Si
• CPC Class Codes: G02F 2202/105 single crystal Si
• CPC Class Codes: G02F 2203/50 Phase-only modulation
• CPC Class Codes: H01L 21/22 Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
• CPC Class Codes: H01L 21/308 using masks H01L21/3063, H01L21/3065 take precedence
• CPC Class Codes: H01L 29/66189 with PN junction, e.g. hybrid capacitors
• CPC Class Codes: H01L 29/94 Metal-insulator-semiconductors, e.g. MOS

Abstract

A MOSCAP phase adjuster includes two conductive regions with a thin insulating region therebetween, where charge is accumulated or depleted. In conventional MOSCAP modulators, the conductive and insulating regions are superposed layers, extending horizontally parallel to the substrate, which limits waveguide design and mode confinement, resulting in reduced phase shift performance. An improved MOSCAP phase adjuster and method of fabricating a MOSCAP phase adjuster includes depositing the material for the second conductive region beside and over top of the first conductive region after oxidation, and selectively etching the material to form the second conductive region.

Claims

1. A phase adjuster device comprising:

a substrate;

a first conductive region on the substrate including a first n or p dopant material at a first doping level;

a first contact region on the substrate, adjacent to the first conductive region, including the first dopant material at a second, higher, doping level;

a second conductive region including a second n or p dopant material, opposite the first dopant material, at a second doping level;

a second contact region on the substrate, adjacent to the first conductive region, including the second dopant material at a second, higher, doping level; and

an insulator layer extending perpendicularly from the substrate between the first conductive region and the second conductive region;

wherein the second conductive region includes a raised spacer portion extending upwardly beyond the first conductive region and at least partially across the top of the first conductive region, wherein the second conductive region also extends completely across the top of the first conductive region.

2. The device according to claim 1, wherein the insulating layer also extends across the top of the first conductive region between the first and second conductive regions.

3. The device according to claim 1, wherein the insulating layer comprises an oxidized layer of the first conductive region.

4. The device according to claim 3, wherein the insulator layer comprises a dielectric.

5. The device according to claim 4, wherein the insulator layer comprises a same material as the substrate.

6. The device according to claim 5, wherein the insulator layer comprises silicon dioxide.

7. The device according to claim 1, wherein the second conductive region comprises a metal or metal-like material.

8. The device according to claim 7, wherein the second conductive region comprises doped poly-silicon.

9. The device according to claim 8, wherein the first conductive region comprises doped silicon.