Digital-to-time converter, time-to-digital converter, and converting method using the same
First Claim
1. A digital-to-time converter, comprising:
- a plurality of delay stages connected in series, wherein each of the plurality of delay stages comprises;
an input circuit, having a first input terminal, a second input terminal and a first output terminal, configured to receive a clock signal through the first input terminal, receive a digital control signal through the second input terminal, generate an output signal according to the clock signal and the digital control signal, and output the output signal to the first output terminal of the input circuit; and
a delay circuit, coupled to the input circuit in series, and configured to receive the output signal and an input signal, and generate a delay signal according to the output signal and the input signal, wherein the delay signal indicates a time interval corresponding to the digital control signal.
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Accused Products
Abstract
A digital-to-time converter (DTC) includes a plurality of delay stages connected in series, in which each of the plurality of delay stages includes an input circuit and a delay circuit. The input circuit has a first input terminal, a second input terminal and a first output terminal, and is configured to receive a clock signal through the first input terminal, receive a digital control signal through the second input terminal, generate an output signal according to the clock signal and the digital control signal, and output the output signal to the first output terminal of the input circuit. The delay circuit is coupled to the input circuit in series, and is configured to receive the output signal and an input signal, and generate a delay signal according to the output signal and the input signal. The delay signal indicates a time interval corresponding to the digital control signal.
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Citations
20 Claims
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1. A digital-to-time converter, comprising:
a plurality of delay stages connected in series, wherein each of the plurality of delay stages comprises; an input circuit, having a first input terminal, a second input terminal and a first output terminal, configured to receive a clock signal through the first input terminal, receive a digital control signal through the second input terminal, generate an output signal according to the clock signal and the digital control signal, and output the output signal to the first output terminal of the input circuit; and a delay circuit, coupled to the input circuit in series, and configured to receive the output signal and an input signal, and generate a delay signal according to the output signal and the input signal, wherein the delay signal indicates a time interval corresponding to the digital control signal. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A converting method adapted to a digital-to-time converter having a plurality of delays stages, each of the plurality of delay stages having an input circuit and a delay circuit, the converting method comprising:
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providing a clock signal to a first input terminal of the input circuit; providing a digital control signal to a second input terminal of the input circuit; performing a first logic operation to the clock signal and the digital control signal to generate an output signal; providing an input signal and the output signal to the delay circuit; performing a second logic operation to the input signal and the output signal to generate a delay signal, wherein the delay signal indicates a time interval corresponding to the digital control signal. - View Dependent Claims (9, 10, 11)
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12. A time-to-digital converter, comprising:
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a plurality of stages connected in series, wherein each of the plurality of stages comprises; a delay circuit, configured to receive a first clock signal and delay the first clock signal to generate a delay clock signal; a sampling circuit, configured to receive a second clock signal, a digital control signal and the delay clock signal, and perform a sampling operation to sample the delay clock signal according to the second clock signal and the digital control signal to generate a digital output signal, wherein a frequency of the first clock signal is greater than a frequency of the second clock signal, and the sampling circuit of each of the plurality of stages is activated or deactivated according to the digital control signal. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20)
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Specification