Voltage select circuit

• US 10,642,294 B1
• Filed: 12/19/2018
• Issued: 05/05/2020
• Est. Priority Date: 12/19/2018
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Mathew, Anu, Zhang, Xu
• Primary Examiner(s): Tra, Anh Q
• Application Number:
  US16/224,932
• Time in Patent Office: 503 Days
• Field of Search: 327407, 327408, 327530
• CPC Class Codes: G01R 19/16528 using digital techniques or performing arithmetic operations using digital techniques to measure a voltage or a current, see G01R19/25
• CPC Class Codes: G05F 1/562 with a threshold detection shunting the control path of the final control device
• CPC Class Codes: G06F 1/266 Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: H03K 17/30 Modifications for providing a predetermined threshold before switching shaping pulses by thresholding H03K5/08
• CPC Class Codes: H03K 17/302 in field-effect transistor switches
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00

Abstract

One example discloses a voltage select circuit, comprising: a first input configured to receive a first input voltage; a second input configured to receive a second input voltage; a first diode having a first polarity coupled to the first input; a second diode having a first polarity coupled to the second input; an output coupled to a second polarity of both the first and second diodes; a diode bypass circuit coupled to the first input and the output in parallel with the first diode, and coupled to the second input; and wherein the bypass circuit is configured to pass the first input voltage to the output if an absolute value of the second input voltage is less than a voltage drop of the second diode.

Claims

1. Voltage select circuit, comprising:

a first input configured to receive a first input voltage;

a second input configured to receive a second input voltage;

a first diode having a first polarity coupled to the first input;

a second diode having a first polarity coupled to the second input;

an output coupled to a second polarity of both the first and second diodes;

a diode bypass circuit coupled to the first input and the output in parallel with the first diode, and coupled to the second input;

wherein the bypass circuit is configured to pass the first input voltage to the output if an absolute value of the second input voltage is less than a voltage drop of the second diode;

a third diode coupled between the diode bypass circuit and a threshold control voltage;

wherein the threshold control voltage is configured to set a constant voltage; and

wherein the bypass circuit is configured to pass the first input voltage to the output if the absolute value of the second input voltage is less than the voltage drop of the second diode minus the constant voltage.

2. The device of claim 1:

wherein the first polarity is a positive polarity;

wherein the second polarity is a negative polarity; and

wherein a more positive of the first and second input voltages is coupled to the output.

3. The device of claim 1:

wherein the first polarity is a negative polarity;

wherein the second polarity is a positive polarity; and

wherein a more negative of the first and second input voltages is coupled to the output.

4. The device of claim 1:

wherein a maximum absolute value of a magnitude of the first input voltage is less than the absolute value of a magnitude of the second voltage.

5. The device of claim 1:

wherein a maximum value of the first input voltage is less than a maximum value of the second voltage.

6. The device of claim 1:

wherein a minimum value of the first input voltage is greater than a minimum value of the second voltage.

7. The device of claim 1:

wherein the bypass circuit includes a MOS device having a drain, source and gate;

wherein the gate of the MOS device is coupled to the second input;

wherein the drain is coupled to the first input; and

wherein the source is coupled to the output.

8. The device of claim 7:

wherein the MOS device is a PMOS device configured to pass the first input voltage to the output if a voltage at the gate is less than or equal to zero volts.

9. The device of claim 7:

wherein the MOS device is a PMOS device configured to pass the first input voltage to the output if the second input voltage is less than or equal to zero volts.

10. The device of claim 7:

wherein the MOS device is an enhancement mode MOS device.

11. The device of claim 1:

wherein the MOS device is an extended-drain MOS device.

12. The device of claim 7:

wherein the third diode is coupled between the gate and the second input;

wherein the third diode is configured to limit a voltage at the gate from the second input voltage on the second input.

13. The device of claim 7:

further comprising a resistor coupled between the gate and a reference potential;

wherein the resistor is configured to clamp a voltage at the gate to less than a MOS device breakdown voltage.

14. The device of claim 1:

wherein the bypass circuit includes a PMOS device having a drain, source and gate;

wherein the gate of the PMOS device is coupled to the second input;

wherein the drain is coupled to the first input;

wherein the source is coupled to the output; and

wherein the constant voltage less than or equal to a threshold voltage of the PMOS device.

15. The device of claim 1:

wherein the third diode is coupled between the diode bypass circuit and the second input.

16. Voltage select circuit in a USB signaling system, comprising:

a first input configured to receive a first input voltage;

a second input configured to receive a second input voltage;

a first diode having a first polarity coupled to the first input;

a second diode having a first polarity coupled to the second input;

an output coupled to a second polarity of both the first and second diodes;

a diode bypass circuit coupled to the first input and the output in parallel with the first diode, and coupled to the second input;

wherein the bypass circuit is configured to pass the first input voltage to the output if an absolute value of the second input voltage is less than a voltage drop of the second diode;

a third diode coupled between the diode bypass circuit and a threshold control voltage;

wherein the threshold control voltage is configured to set a constant voltage;

wherein the bypass circuit is configured to pass the first input voltage to the output if the absolute value of the second input voltage is less than the voltage drop of the second diode minus the constant voltage; and

wherein the output is coupled to a current generation circuit configured to output a gate bias for the USB signaling system.