Fast-enable current source

• US 10,642,303 B1
• Filed: 03/14/2019
• Issued: 05/05/2020
• Est. Priority Date: 03/14/2019
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Inventors: Pauk, Ondrej, Pigott, John
• Primary Examiner(s): Nguyen, Hai L
• Application Number:
  US16/354,147
• Time in Patent Office: 418 Days
• CPC Class Codes: G05F 1/56 using semiconductor devices in series with the load as final control devices G05F1/461 takes precedence
• CPC Class Codes: G05F 3/20 using diode- transistor combinations G05F3/18 takes precedence
• CPC Class Codes: G05F 3/262 using field-effect transistors only
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors

Abstract

A method for fast-enabling a current source includes conducting a first current through a first branch including a first transistor connected in series with a first switch, in response to enabling the first switch with an enable signal. A first charge is removed from a bias rail with a first capacitance between a first gate and a first source of the first transistor. A second current is conducted through a second branch including a second switch connected in series with a second transistor, in response to enabling the second switch with the enable signal. A second charge is added to the bias rail with a second capacitance between a second drain and a second gate of the second transistor, wherein the first gate and the second gate are connected to the bias rail and biased by the mirror reference voltage.

Claims

1. A fast-enable current source comprising:

a bias chain configured to generate a mirror reference voltage on a bias rail;

a first branch comprising a first transistor having a first drain connected to a first node, a first source connected to a first switch, and a first gate connected to the bias rail, the first switch configured to short the first source to a second node in response to an enable signal;

a first capacitance between the first gate and the first source;

a second branch comprising a second transistor having a second drain connected to a second switch, a second source connected to the second node, and a second gate connected to the bias rail, the second switch configured to short the second drain to the first node in response to the enable signal; and

a second capacitance between the second drain and the second gate, wherein in response to the enable signal, a first charge removed from the bias rail by the first capacitor is offset by a second charge added to the bias rail by the second capacitor.

2. The fast-enable current source of claim 1 wherein the first charge equals the second charge, and a first width of the first transistor divided by a second width of the second transistor defines an optimal transistor ratio.

3. The fast-enable current source of claim 2 wherein the optimal transistor ratio is one half, wherein each of the transistors of the fast-enable current source comprise n-channel field effect transistors.

4. The fast-enable current source of claim 1 wherein the first switch comprises an n-channel field effect transistor comprising a first switch drain connected to the first source, a first switch gate connected to the enable signal configured to enable the first switch, and a first switch source connected to the second node.

5. The fast-enable current source of claim 1 wherein the second switch comprises a high-voltage n-channel field effect transistor comprising a second switch drain connected to the first node, a second switch gate connected to the enable signal configured to enable the second switch, and a second switch source connected to the second drain.

6. The fast-enable current source of claim 1 wherein the bias chain comprises a bias transistor comprising a bias drain connected to a current source, a bias gate connected to the bias drain and the bias rail, and a bias source connected to the second node.

7. The fast-enable current source of claim 6 further comprising a bias compensation device connected between the bias source and the second node, wherein the bias compensation device has a same voltage drop as the first switch when the first switch is enabled.

8. The fast-enable current source of claim 1 further comprising a protection device connected between the first node and the first drain, wherein the protection device has a same voltage drop as the second switch when the second switch is enabled.

9. The fast-enable current source of claim 1 further comprising a compensation device connected between the second source and the second node, wherein the compensation device has a same voltage drop as the first switch when the first switch is enabled.

10. The fast-enable current source of claim 1 wherein the first capacitance is a first parasitic capacitance of the first transistor, and the second capacitance is a second parasitic capacitance of the second transistor.

11. A method for fast-enabling a current source comprising:

generating a mirror reference voltage on a bias rail;

conducting a first current through a first branch between a first node and a second node, the first branch comprising a first transistor connected in series with a first switch, in response to enabling the first switch with an enable signal;

removing a first charge from the bias rail with a first capacitance between a first gate and a first source of the first transistor, wherein the first gate is biased by the mirror reference voltage;

conducting a second current through a second branch between the first node and the second node, the second branch comprising a second switch connected in series with a second transistor, in response to enabling the second switch with the enable signal; and

adding a second charge to the bias rail with a second capacitance between a second drain and a second gate of the second transistor, wherein the second gate is biased by the mirror reference voltage.

12. The method of claim 11 further comprising determining an optimal transistor ratio by dividing a first width of the first transistor by a second width of the second transistor, wherein the optimal transistor ratio results in the first charge being equal to the second charge.

13. The method of claim 12 wherein determining the optimal transistor ratio results in the first width being half of the second width, wherein each of the transistors of the current source comprises n-channel field effect transistors.

14. The method of claim 11 further comprising compensating for an impedance of the second switch with a protection device between the first node and the first drain, wherein the protection device has a same voltage drop as the second switch when the second switch is enabled.

15. The method of claim 11 further comprising compensating for an impedance of the first switch with a compensation device between the second source and the second node, wherein the compensation device has a same voltage drop as the first switch when the first switch is enabled.

16. The method of claim 11 wherein generating the mirror reference voltage comprises sourcing a current through a bias transistor comprising a bias drain connected to a current source, a bias gate connected to the bias drain and the bias rail, and a bias source connected to the second node.

17. The method of claim 16 further comprising compensating for an impedance of the first switch with a bias compensation device connected between the bias source and the second node, wherein the bias compensation device has a same voltage drop as the first switch when the first switch is enabled.

18. A fast-enable current source comprising:

a first branch comprising a first transistor having a first drain connected to a protection device, a first source connected to a first switch, and a first gate connected to a bias rail, the protection device connected to a first node, the first switch configured to short the first source to a second node in response to an enable signal;

a first parasitic capacitance between the first gate and the first source;

a second branch comprising a second transistor having a second drain connected to a second switch, a second source connected to a compensation device, and a second gate connected to the bias rail, the compensation device connected to the second node, the second switch configured to short the second drain to the first node in response to the enable signal; and

a second parasitic capacitance between the second drain and the second gate, wherein in response to the enable signal, a first charge removed from the bias rail by the first capacitor is offset by a second charge added to the bias rail by the second capacitor.

19. The fast-enable current source of claim 18 wherein the protection device has a same voltage drop as the second switch when the second switch is enabled.

20. The fast-enable current source of claim 18 wherein the compensation device has a same voltage drop as the first switch when the first switch is enabled.