Gate driver circuit for reducing deadtime inefficiencies

• US 10,642,306 B1
• Filed: 05/08/2019
• Issued: 05/05/2020
• Est. Priority Date: 05/08/2019
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Shankar, Krishnamurthy Ganapathi
• Primary Examiner(s): Kim, Jung
• Application Number:
  US16/406,104
• Time in Patent Office: 363 Days
• CPC Class Codes: G05F 3/267 using both bipolar and field-effect technology
• CPC Class Codes: H02H 7/1213 for DC-DC converters
• CPC Class Codes: H02M 1/08 Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: H02P 7/04 by means of a H-bridge circuit
• CPC Class Codes: H03K 17/04123 in field-effect transistor switches
• CPC Class Codes: H03K 17/063 in field-effect transistor switches
• CPC Class Codes: H03K 17/163 Soft switching
• CPC Class Codes: H03K 17/62 Switching arrangements with several input- output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00
• CPC Class Codes: H03K 2217/0036 Means reducing energy consumption
• CPC Class Codes: H03K 2217/0081 Power supply means, e.g. to the switch driver
• CPC Class Codes: Y02P 80/10 Efficient use of energy, e.g. using compressed air or pressurized fluid as energy carrier

Abstract

A driver circuit comprises a first buffer receiving a control signal, and a first transistor coupled to first buffer and an output. A second transistor is coupled to a first current mirror and the output. A third transistor is coupled to the output and an inverter. A fourth transistor receives the inverter'"'"'s output at its control input and is coupled to the output. A fifth transistor is coupled to third transistor. The second, third, and fifth transistors receive supply voltage at their respective control inputs. A sixth transistor receives the control signal'"'"'s inverse at its control input and is coupled to fifth transistor and a second current mirror. A current source is coupled to second current mirror and a second buffer. A seventh transistor receives the second buffer'"'"'s output at its control input and is coupled to first buffer. An eighth transistor is coupled to first buffer and seventh transistor.

Claims

1. A driver circuit, comprising:

a first buffer configured to receive a first control signal;

a first transistor coupled to an output node of the driver circuit, wherein a current terminal of the first transistor is configured to receive an output of the first buffer;

a first current mirror;

a second transistor coupled to the first current mirror and the output node, wherein a control input of the second transistor is configured to receive a supply voltage;

a third transistor coupled to the output node and an inverter, wherein a control input of the third transistor is configured to receive the supply voltage;

a fourth transistor coupled to the output node, wherein a control input of the fourth transistor is configured to receive an output of the inverter;

a fifth transistor coupled to the third transistor, wherein a control input of the fifth transistor is configured to receive the supply voltage;

a sixth transistor coupled to the fifth transistor and a second current mirror, wherein a control input of the sixth transistor is configured to receive a second control signal and wherein the second control signal is an inverse of the first control signal;

a current source coupled to the second current mirror and a second buffer;

a seventh transistor coupled to the first buffer, wherein a control input of the seventh transistor is configured to receive an output of the second buffer; and

an eighth transistor coupled to the first buffer and the seventh transistor.

2. The driver circuit of claim 1, wherein the first, sixth, seventh, and eighth transistors are n-type metal oxide semiconductor field effect transistors and the second, third, fourth, and fifth transistors are p-type metal oxide semiconductor field effect transistors.

3. The driver circuit of claim 1, wherein the first, second, third, fourth, fifth, sixth, seventh, and eighth transistors are bipolar junction transistors.

4. The driver circuit of claim 1, wherein a control input of the eighth transistor is configured to receive a third control signal from a charge pump protection circuit configured to prevent charge pump collapse.

5. The driver circuit of claim 1, wherein the first current mirror comprises a ninth transistor and a tenth transistor coupled to the ninth transistor.

6. The driver circuit of claim 5, wherein a current terminal of the ninth transistor and a current terminal of the tenth transistor are coupled to a supply voltage node.

7. The driver circuit of claim 5, wherein the ninth and tenth transistors are bipolar junction transistors.

8. The driver circuit of claim 5, wherein the ninth and tenth transistors are p-type metal oxide semiconductor field effect transistors.

9. The driver circuit of claim 5, further comprising an eleventh transistor coupled to the first current mirror and a charge pump protection circuit, wherein a control input of the eleventh transistor is configured to receive the first control signal and wherein a current terminal of the eleventh transistor is coupled to a control input of the ninth transistor and a control input of the tenth transistor.

10. The driver circuit of claim 9, wherein a current output by the first current mirror varies based on an impedance of the charge pump protection circuit.

11. The driver circuit of claim 1, wherein the second current mirror comprises a twelfth transistor and a thirteenth transistor coupled to the twelfth transistor.

12. The driver circuit of claim 11, wherein the twelfth and thirteenth transistors are bipolar junction transistors.

13. The driver circuit of claim 11, wherein the twelfth and thirteenth transistors are n-type metal oxide semiconductor field effect transistors.

14. The driver circuit of claim 1, wherein a current terminal of the fourth transistor is coupled to a supply voltage node.