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Computer device and power abnormality detection method for a computer device

  • US 10,642,334 B2
  • Filed: 04/03/2018
  • Issued: 05/05/2020
  • Est. Priority Date: 11/15/2017
  • Status: Active Grant
First Claim
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1. A computer device coupled to a peripheral device, comprising:

  • a microprocessor;

    a voltage converter circuit, coupled to the microprocessor and configured to convert a first voltage of a system power of the computer device into a second voltage;

    a control circuit, coupled to the microprocessor and the voltage converter circuit and configured to control supply of the second voltage; and

    a detection circuit, coupled to the microprocessor and a power detection pin and configured to detect whether a power abnormality at the peripheral device has occurred, wherein the power detection pin is coupled to the peripheral device, andwherein when confirming that the system power is being supplied normally, the microprocessor is configured to generate a first enable signal to enable the voltage converter circuit, andwhen confirming that the voltage converter circuit functions normally, the microprocessor is configured to generate a second enable signal to enable the detection circuit, and the detection circuit is configured to generate a first detection signal based on a corresponding detection result, andwherein the microprocessor is further configured to determine whether to supply the second voltage to the peripheral device according to the first detection signal, when the first detection signal indicates that a power abnormality has not occurred at the peripheral device, the microprocessor generates a third enable signal to enable the control circuit, such that the second voltage is supplied to the peripheral device via the control circuit,wherein the voltage converter circuit is further configured to detect whether the second voltage is supplied normally and generate a third detection signal based on a corresponding detection result, and the voltage converter circuit is further configured to detect whether an output current thereof is overloaded and generate a fourth detection signal based on a corresponding detection result, and wherein the microprocessor is further configured to generate the second enable signal according to the third detection signal and the fourth detection signal.

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