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Clock adjustment for voltage droop

  • US 10,642,336 B2
  • Filed: 07/12/2016
  • Issued: 05/05/2020
  • Est. Priority Date: 07/12/2016
  • Status: Active Grant
First Claim
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1. A method comprising:

  • in response to detecting a voltage drop at a processor, modifying a first set of enable signals provided from a clock control module to generate a modified first set of enable signals using a set of stretch enable signals provided from a stretch control module coupled directly to a voltage detection module andgenerating a first clock signal based on the modified first set of enable signals, wherein generating the first clock signal comprises;

    selecting a plurality of clock signals based on the modified first set of enable signals; and

    logically combining the selected plurality of clock signals to generate the first clock signal;

    modifying a second set of enable signals to generate a modified second set of enable signals, in response to detecting the voltage drop at the processor; and

    generating a second clock signal based on the modified second set of enable signals.

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