Clock adjustment for voltage droop
First Claim
1. A method comprising:
- in response to detecting a voltage drop at a processor, modifying a first set of enable signals provided from a clock control module to generate a modified first set of enable signals using a set of stretch enable signals provided from a stretch control module coupled directly to a voltage detection module andgenerating a first clock signal based on the modified first set of enable signals, wherein generating the first clock signal comprises;
selecting a plurality of clock signals based on the modified first set of enable signals; and
logically combining the selected plurality of clock signals to generate the first clock signal;
modifying a second set of enable signals to generate a modified second set of enable signals, in response to detecting the voltage drop at the processor; and
generating a second clock signal based on the modified second set of enable signals.
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Accused Products
Abstract
A processor adjusts frequencies of one or more clock signals in response to a voltage droop at the processor. The processor generates at least one clock signal by generating a plurality of base clock signals, each of the base clock signals having a common frequency but a different phase. The processor also generates a plurality of enable signals, wherein each enable signal governs whether a corresponding one of the base clock signals is used to generate the clock signal. The enable signals therefore determine the frequency of the clock signal. In response to detecting a voltage droop, the processor adjusts the enable signals used to generate the clock signal, thereby reducing the frequency of the clock signal droop.
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Citations
16 Claims
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1. A method comprising:
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in response to detecting a voltage drop at a processor, modifying a first set of enable signals provided from a clock control module to generate a modified first set of enable signals using a set of stretch enable signals provided from a stretch control module coupled directly to a voltage detection module and generating a first clock signal based on the modified first set of enable signals, wherein generating the first clock signal comprises; selecting a plurality of clock signals based on the modified first set of enable signals; and logically combining the selected plurality of clock signals to generate the first clock signal; modifying a second set of enable signals to generate a modified second set of enable signals, in response to detecting the voltage drop at the processor; and generating a second clock signal based on the modified second set of enable signals. - View Dependent Claims (2, 3, 4, 5)
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6. A method, comprising:
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generating a first set of enable signals at a clock control module; generating a first clock signal at a first frequency based on the first set of enable signals; providing the first clock signal at the first frequency to a processor; and in response to detecting a voltage drop at the processor, modifying the first set of enable signals using a set of stretch enable signals provided from a stretch control module coupled directly to a voltage detection module to change a frequency of the first clock signal from the first frequency to a second frequency, the second frequency different from the first frequency; generating a second set of enable signals; generating a second clock signal at a third frequency based on the second set of enable signals; providing the second clock signal at the second frequency to the processor; and in response to detecting the voltage drop at the processor, modifying the first set of enable signals to change a frequency of the second clock signal from the third frequency to a fourth frequency, the fourth frequency different from the third frequency. - View Dependent Claims (7, 8, 9, 10)
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11. A processor comprising:
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a voltage detection module to detect a voltage drop at the processor; a first clock generation module to receive a first set of enable signals output by a clock control module and a first plurality of clock signals, the first clock module to generate a first clock signal based on the first set of enable signals from the clock control module and the plurality of clock signals; and a stretch control module coupled directly to the voltage detection module and coupled to the first clock module to modify the first set of enable signals in response to the voltage detection module indicating the voltage drop, wherein in order to modify the first set of enable signals, the stretch control module provides a set of stretch enable signals to an input of the first clock module; a second clock generation module to receive a second set of enable signals and the first plurality of clock signals, the second clock generation module to generate a second clock signal based on the second set of enable signals and the plurality of clock signals; and the stretch control module to modify the second set of enable signals in response to the voltage detection module indicating the voltage drop. - View Dependent Claims (12, 13, 14, 15, 16)
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Specification