Hierarchical power management unit for low power and low duty cycle devices

• US 10,642,338 B2
• Filed: 09/28/2017
• Issued: 05/05/2020
• Est. Priority Date: 09/28/2017
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kurian, Dileep J., Deshmukh, Pranjali S., Kabisthalam Muthukumar, Sriram, Gupta, Ankit, Karnik, Tanay, Arditti Ilitzky, David, Bhandari, Saurabh
• Primary Examiner(s): Stoynov, Stefan
• Application Number:
  US15/719,483
• Publication Number:
  US 20190094949A1
• Time in Patent Office: 950 Days
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An apparatus is provided which comprises: a first Power Management Unit (PMU); and a second PMU, wherein the first PMU is to manage transition of the apparatus from a low power state to a first active state, wherein the second PMU is to manage transition of the apparatus from the first active state to a second active state, and wherein the second PMU is to be powered down while the apparatus is to be in the low power state.

Claims

1. An apparatus comprising:

a first Power Management Unit (PMU); and

a second PMU,

wherein the first PMU is to manage transition of the apparatus from a low power state to a first active state,

wherein the second PMU is to manage transition of the apparatus from the first active state to a second active state,

wherein the second PMU is to be powered down while the apparatus is to be in the low power state,

wherein while the apparatus is in the first active state, the first PMU is to issue a warning in response to a charge level of a battery being less than a non-critical threshold, and

wherein the second PMU is to decide to pause or abort one or more pending tasks, and to return control to the first PMU, to enable the first PMU to transition the apparatus to the low power state.

2. The apparatus of claim 1, further comprising:

a processor,

wherein the second PMU is to manage a dynamic voltage frequency scaling for the processor.

3. The apparatus of claim 1, wherein:

the low power state is a first low power state; and

the first PMU is to manage transition of the apparatus from the first low power state to a second low power state.

4. The apparatus of claim 1, further comprising:

a first die comprising the first PMU; and

a second die comprising the second PMU,

wherein the first die is to consume relatively low power compared to the second die, and

wherein power to the second die is to be shut off while the apparatus is to be in the low power state.

5. The apparatus of claim 4, further comprising:

the battery; and

an energy source to generate power,

wherein the first die comprises circuitry to harvest power from the energy source, to recharge the battery.

6. The apparatus of claim 4, wherein the second die comprises a processor to implement one or more functionalities of the apparatus.

7. The apparatus of claim 1, wherein:

while the apparatus is in the first active state and in response to a charge level of the battery being less than a critical threshold, the first PMU is to override the second PMU and to force the apparatus to transition to the low power state.

8. The apparatus of claim 1, further comprising:

a first subsystem comprising the first PMU;

a second subsystem comprising the second PMU and one or more components; and

a power rail to supply power to the second subsystem,

wherein the first PMU is to power the power rail to a voltage specified by the second PMU.

9. The apparatus of claim 1, further comprising:

a first subsystem comprising the first PMU;

a second subsystem comprising the second PMU;

a power rail to supply power to the second subsystem; and

a plurality of voltage domains within the second subsystem supplied by the power rail,

wherein the second PMU is to control levels of voltage supplied from the power rail to the individual ones of the plurality of voltage domains.

10. The apparatus of claim 1, wherein:

the apparatus has a low duty cycle of operation; and

the apparatus is a Net zero energy (NZE) device.

11. A system comprising:

a battery;

a memory to store instructions;

a processor coupled to the memory;

first power management circuitry to control a voltage level and/or a frequency level for the processor;

second power management circuitry to control switching on and/or switching off of the first power management circuitry, wherein while the processor is in an active state, the second power management circuitry is to issue a warning in response to a charge level of the battery being less than a non-critical threshold; and

wherein the first management circuitry is to decide to pause or abort one or more unresolved tasks, and to return control to the second management circuitry, to enable the second power management circuit to transition the processor to the low power state; and

a wireless interface to allow the processor to communicate with another device.

12. The system of claim 11, wherein:

the first power management circuitry is to manage transition between two or more active states of the system.

13. The system of claim 11, wherein:

the second power management circuitry comprises a Finite State Machine (FSM) to manage transition between a low power state and an active state, and between two or more low power states of the system.

14. The system of claim 11, wherein the first power management circuitry is to manage dynamic voltage and frequency scaling (DVFS) for the processor.

15. The system of claim 11, wherein:

the second power management circuitry is to remain switched on during one or more low power states of the processor; and

the first power management circuitry is to remain switched off during the one or more low power states of the processor, and to remain switched on during one or more active states of the system.

16. A device comprising:

hierarchical power management architecture comprising;

first power management circuitry that is to remain switched on during one or more low power states and one or more active states; and

second power management circuitry that is to remain switched off during the one or more low power states and remain switched on during the one or more active states,

wherein the device has a low duty cycle of operation, wherein while the device is in an active state, the first power management circuitry is to issue a warning in response to a charge level of a battery being less than a non-critical threshold, and

wherein the second power management circuitry is to decide to pause or abort one or more unresolved tasks, and to return control to the first power management circuitry, to enable the first power management circuitry to transition the device to the low power state.

17. The device of claim 16, wherein:

the first power management circuitry consumes relatively less power to remain switched on, compared to power consumed by the second power management circuitry to remain switched on.

18. The device of claim 16, further comprising:

a first die comprising the first power management circuitry; and

a second die comprising the second power management circuitry,

wherein power supply to the second die is to be switched off during the one or more low power states.

19. The device of claim 16, wherein the device is a Net zero energy (NZE) device.