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Rotational graphics sub-slice and execution unit power down to improve power performance efficiency

  • US 10,642,340 B2
  • Filed: 05/08/2017
  • Issued: 05/05/2020
  • Est. Priority Date: 09/29/2012
  • Status: Active Grant
First Claim
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1. A processor comprising:

  • a plurality of processor cores, wherein the processor comprises a first portion and a second portion, wherein the first portion comprises one or more of the plurality of processor cores and a level 2 (L2) cache, wherein the second portion comprises a level 3 (L3) cache;

    at least one voltage regulator logic circuitry to control supply of voltage to one or more of the plurality of processor cores;

    on-chip power management logic circuitry to cause power-gating amongst the first portion or the second portion of the processor based at least in part on an indication to reduce power consumption of the first portion or the second portion; and

    one or more on-chip sensors to sense one or more value variations in one or more of;

    temperature, voltage, current, and activity for one or more of the plurality of processor cores, wherein the indication to reduce power consumption is based on the one or more value variations, wherein the on-chip power management logic circuitry is to cause rotation of power-gating amongst one or more portions of the plurality of processor cores, wherein the on-chip power management logic circuitry is to cause a first time period spent in a first rotation to have a different period than a second time period spent in a second rotation.

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