Rotational graphics sub-slice and execution unit power down to improve power performance efficiency

• US 10,642,340 B2
• Filed: 05/08/2017
• Issued: 05/05/2020
• Est. Priority Date: 09/29/2012
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Hurd, Linda L.
• Primary Examiner(s): Abbaszadeh, Jaweed A
• Assistant Examiner(s): Corcoran, Brian J
• Application Number:
  US15/589,748
• Publication Number:
  US 20170315607A1
• Time in Patent Office: 1,093 Days
• CPC Class Codes: G06F 1/3278 Power saving in modem or I/O interface
• CPC Class Codes: G06F 1/3293 by switching to a less power-consuming processor, e.g. sub-CPU
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Methods and apparatus relating to rotational graphics sub-slice and Execution Unit (EU) power down to improve power performance efficiency are described. In one embodiment, power-gating is rotated amongst single sub-slices within each slice of a plurality of slices based on an indication to reduce power consumption of a computational logic. The computational logic includes the plurality of slices and each of the plurality of slices includes a plurality of sub-slices to perform one or more computations. Other embodiments are also disclosed and claimed.

Claims

1. A processor comprising:

a plurality of processor cores, wherein the processor comprises a first portion and a second portion, wherein the first portion comprises one or more of the plurality of processor cores and a level 2 (L2) cache, wherein the second portion comprises a level 3 (L3) cache;

at least one voltage regulator logic circuitry to control supply of voltage to one or more of the plurality of processor cores;

on-chip power management logic circuitry to cause power-gating amongst the first portion or the second portion of the processor based at least in part on an indication to reduce power consumption of the first portion or the second portion; and

one or more on-chip sensors to sense one or more value variations in one or more of;

temperature, voltage, current, and activity for one or more of the plurality of processor cores, wherein the indication to reduce power consumption is based on the one or more value variations, wherein the on-chip power management logic circuitry is to cause rotation of power-gating amongst one or more portions of the plurality of processor cores, wherein the on-chip power management logic circuitry is to cause a first time period spent in a first rotation to have a different period than a second time period spent in a second rotation.

2. The processor of claim 1, wherein the on-chip power management logic circuitry is to cause power-gating of a portion of a first processor core of the plurality of processor cores while allowing turbo operation of a second processor core of the plurality of processor cores.

3. The processor of claim 1, wherein the processor is to comprise a Graphics Processing Unit (GPU).

4. The processor of claim 1, wherein the one or more on-chip sensors are to further detect one or more of:

dynamic capacitance, frequency, and power consumption.

5. The processor of claim 1, wherein the on-chip power management logic is to cause rotation of power-gating amongst one or more portions of the plurality of processor cores, wherein residency in each rotation of power-gating is capable to differ for portions of the plurality of processor cores.

6. The processor of claim 1, wherein the first portion is to comprise a plurality of slices, wherein each of the plurality of slices is to comprise a plurality of sub-slices.

7. The processor of claim 6, wherein the on-chip power management logic is to cause each powered down sub-slice within each slice of the plurality of slices to be powered up in response to expiration of a timer.

8. The processor of claim 6, wherein each sub-slice is to comprise one or more execution units.

9. The processor of claim 8, wherein each of the one or more execution units is to comprise a plurality of processing elements.

10. The processor of claim 9, wherein each of the plurality of processing elements is to comprise one or more ALUs (Arithmetic Logic Units), wherein each of the one or more ALUs is to perform the role of a shader processor.

11. The processor of claim 1, wherein the on-chip power management logic is to cause rotation of power-gating amongst one or more portions of the plurality of processor cores based on information detected at the one or more on-chip sensors.

12. The processor of claim 1, wherein one or more of the first portion and second portion, one or more voltage regulators, the on-chip power management logic, the one or more on-chip sensors, and memory are on a single integrated circuit die.

13. A single chip comprising:

memory controller coupled to memory, the memory to store one or more instructions;

a processor having a plurality of processor cores to execute the one or more instructions, wherein the processor comprises a first portion and a second portion, wherein the first portion comprises one or more of the plurality of processor cores and a level 2 (L2) cache, wherein the second portion comprises a level 3 (L3) cache;

at least one voltage regulator logic circuitry to control supply of voltage to one or more of the plurality of processor cores;

on-chip power management logic circuitry to cause power-gating amongst the first portion or the second portion of the processor based at least in part on an indication to reduce power consumption of the first portion or the second portion; and

one or more on-chip sensors to sense one or more value variations in one or more of;

temperature, voltage, current, and activity for one or more of the plurality of processor cores, wherein the indication to reduce power consumption is based on the one or more value variations, wherein the on-chip power management logic circuitry is to cause rotation of power-gating amongst one or more portions of the plurality of processor cores, wherein the on-chip power management logic circuitry is to cause a first time period spent in a first rotation to have a different period than a second time period spent in a second rotation.

14. The chip of claim 13, wherein the on-chip power management logic circuitry is to cause power-gating of a portion of a first processor core of the plurality of processor cores while allowing turbo operation of a second processor core of the plurality of processor cores.

15. The chip of claim 13, wherein each of the plurality of processor cores are to comprise an execution unit.

16. The chip of claim 13, wherein the on-chip power management logic is to cause rotation of power-gating amongst one or more portions of the plurality of processor cores, wherein residency in each rotation of power-gating is capable to differ for portions of the plurality of processor cores.

17. The chip of claim 13, wherein the first portion is to comprise a plurality of slices, wherein each of the plurality of slices is to comprise a plurality of sub-slices.

18. A method comprising:

performing, at a processor, one or more computations, wherein the processor comprises a first portion and a second portion, wherein the first portion comprises one or more of a plurality of processor cores and a level 2 (L2) cache, wherein the second portion comprises a level 3 (L3) cache, wherein the processor comprises at least one voltage regulator logic circuitry to control supply of voltage to one or more of the plurality of processor cores; and

causing power-gating, at on-chip power management logic circuitry, amongst the first portion or the second portion of the processor based at least in part on an indication to reduce power consumption of the first portion or the second portion, wherein the indication is based on one or more value variations, detected at one or more on-chip sensors, in one or more of;

temperature, voltage, current, and activity for one or more of the plurality of processor cores, wherein the on-chip power management logic circuitry causes rotation of power-gating amongst one or more portions of the plurality of processor cores, wherein the on-chip power management logic circuitry causes a first time period spent in a first rotation to have a different period than a second time period spent in a second rotation.

19. The method of claim 18, further comprising the on-chip power management logic circuitry causing power-gating of a portion of a first processor core of the plurality of processor cores while allowing turbo operation of a second processor core of the plurality of processor cores.

20. The method of claim 18, further comprising the on-chip power management logic circuitry causing rotation of power-gating amongst one or more portions of the plurality of processor cores, wherein residency in each rotation of power-gating is capable to differ for portions of the plurality of processor cores.

21. One or more non-transitory computer-readable medium comprising one or more instructions that when executed on at least one processor configure the at least one processor to perform one or more operations to:

perform, at the processor, one or more computations, wherein the processor comprises a first portion and a second portion, wherein the first portion comprises one or more of a plurality of processor cores and a level 2 (L2) cache, wherein the second portion comprises a level 3 (L3) cache, wherein the processor comprises at least one voltage regulator logic circuitry to control supply of voltage to one or more of the plurality of processor cores; and

cause power-gating, at on-chip power management logic circuitry, amongst the first portion or the second portion of the processor based at least in part on an indication to reduce power consumption of the first portion or the second portion, wherein the indication is based on one or more value variations, detected at one or more on-chip sensors, in one or more of;

temperature, voltage, current, and activity for one or more of the plurality of processor cores, wherein the on-chip power management logic circuitry is to cause rotation of power-gating amongst one or more portions of the plurality of processor cores, wherein the on-chip power management logic circuitry is to cause a first time period spent in a first rotation to have a different period than a second time period spent in a second rotation.

22. The one or more non-transitory computer-readable medium of claim 21, further comprising one or more instructions that when executed on the at least one processor configure the at least one processor to perform one or more operations to cause the on-chip power management logic circuitry to cause power-gating of a portion of a first processor core of the plurality of processor cores while allowing turbo operation of a second processor core of the plurality of processor cores.

23. The one or more non-transitory computer-readable medium of claim 21, further comprising one or more instructions that when executed on the at least one processor configure the at least one processor to perform one or more operations to cause the on-chip power management logic circuitry to cause rotation of power-gating amongst one or more portions of the plurality of processor cores, wherein residency in each rotation of power-gating is capable to differ for portions of the plurality of processor cores.