Drive control device for a display having display elements and touch detection electrodes

• US 10,642,405 B2
• Filed: 03/16/2017
• Issued: 05/05/2020
• Est. Priority Date: 04/28/2016
• Status: Active Grant

• Current Assignee: Omnivision TDDI Ontario Limited Partnership
• Original Assignee: Synaptics Japan GK (Synaptics Incorporated)
• Inventors: Kuroiwa, Tsuyoshi, Noto, Takayuki, Takanashi, Mitsunori
• Primary Examiner(s): Awad, Amr A
• Assistant Examiner(s): Lui, Donna V
• Application Number:
  US15/460,773
• Publication Number:
  US 20170315659A1
• Time in Patent Office: 1,146 Days
• Field of Search: None
• CPC Class Codes: G06F 3/0412 Digitisers structurally integrated in a display
• CPC Class Codes: G06F 3/04184 Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally
• CPC Class Codes: G06F 3/043 using propagating acoustic waves
• CPC Class Codes: G06F 3/0446 using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes
• CPC Class Codes: G09G 2310/0202 Addressing of scan or signal lines
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2354/00 Aspects of interface with display user
• CPC Class Codes: G09G 2360/12 Frame memory handling
• CPC Class Codes: G09G 2360/18 Use of a frame buffer in a display terminal, inclusive of the display panel
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3677 suitable for active matrices only

Abstract

The drive control device includes a display control part and a touch control part. The display control part includes a control circuit operable to control first and second frame modes, and a clock pulse generator operable to produce a display line clock signal in synchronization with a display line switching cycle. The control circuit changes display and non-display drive terms in start timing on an individual display frame period basis in the first frame mode. In the second frame mode, each display frame period includes only one display drive term; the display drive term is not interrupted by a non-display drive term halfway. The second frame mode is arranged so that the cycle of the display line clock signal in synchronization with the display line switching cycle is made longer than that in the first frame mode.

Claims

1. A panel driver configured to control a panel having display elements and touch detection electrodes, comprising:

a display controller configured to select a display line out of the display elements and provide a display signal to the display line during a display interval;

a touch controller configured to control the touch detection electrodes during a non-display interval,

wherein the display controller includes a control circuit to control first and second frame modes, and a clock pulse generator (“

CPG”

) to generate a display line clock signal synchronized with a display line switching signal;

wherein;

in the first frame mode, the non-display interval and the display interval are alternately created generated multiple times during a time interval between opposing blanking intervals of each display frame period, and the touch controller is configured to accept touch detection directive during the non-display interval;

in the second frame mode, the non-display interval and the display interval subsequent thereto are generated in a time interval between opposing blanking intervals of each display frame period, and the touch controller does not accept a touch detection directive during the non-display interval; and

in the first frame mode, the control circuit is further configured to change the display interval and the subsequent non-display interval to start timing on an individual display frame period basis for every plurality of display frame periods;

wherein the CPG is configured to output a display line clock signal of a first cycle in the first frame mode, and output a display line clock signal of a second cycle longer than the first cycle in the second frame mode;

wherein the control circuit comprises a first control logic configured to;

count the cycle number of the display line clock signal in each display frame period and, in parallel, sequentially generate produce status signals when the count value reaches the start timing of each of the display and non-display drive intervals in the display frame period, and

output a mode-determination signal indicating whether the status signals are for the first frame mode or the second frame mode; and

wherein;

the touch controller is further configured to receive the status signals and generate touch control signals for touch detection according to the received status signals; and

the control circuit further comprises a second control logic configured to receive the mode-determination signal from the first control logic and, based at least in part on the mode-determination signal, supply the CPG with;

a first control signal when the mode-determination signal indicates the first frame mode, and

a second control signal when the mode-determination signal indicates the second frame mode.

2. The panel driver of claim 1, wherein:

the display controller has a scan line drive circuit operable to output scan line select clock signals for sequentially selecting the scan lines of the display elements, and a signal line drive circuit operable to supply display drive signals to the display elements of the selected scan lines;

the scan line drive circuit is configured to change, in pulse, the scan line select clock signals in synchronization with the display line clock signal;

the signal line drive circuit is configured to switch the display drive signals in synchronization with the display line clock signal; and

the scan line drive circuit is configured to output the scan line select clock signals so that a first interval from a timing of output switching of display drive signals to scan line nonselect pulse change of the scan line select clock signals remains unchanged between a case where the cycle of the display line clock signal is the first cycle and a case where the cycle of the display line clock signal is the second cycle.

3. The panel driver of claim 2, wherein:

the first interval is a difference of a third interval from a second interval;

the scan line drive circuit is configured to change the scan line select clock signals to scan line nonselect pulses when the second interval elapses from the pulse change of the display line clock signal; and

the signal line drive circuit is configured to switch the output of the display drive signals when the third interval elapses from the pulse change of the display line clock signal.

4. The panel driver of claim 2, wherein the control circuit is configured to issue directives for the first and second cycles to the clock pulse generator, issue a directive for a second interval to the scan line drive circuit, and issue a directive for a third interval to the signal line drive circuit.

5. The panel driver of claim 4, wherein the control circuit is configured to rewritably set a clock control register with first control data to specify the first cycle, second control data to specify the second cycle, third control data to specify the second interval, and fourth control data to specify the third interval, and

the control circuit is configured to issue directives for the first cycle, the second cycle, the second interval and the third interval based on the first to fourth control data set on the clock control register.

6. The panel driver of claim 5, further comprising a microprocessor operable to determine a touch or no touch based on signals obtained by the touch controller in during touch detection,

wherein the microprocessor is configured to set the first to fourth control data on the clock control register.

7. The panel driver of claim 1, wherein:

the display controller has a buffer memory into which display data are written in synchronization with an external horizontal synchronizing signal of a cycle longer than the second cycle, and from which display data are read in synchronization with the display line clock signal;

the first cycle is a cycle of sufficient length to insure that an intermittent read action at a speed faster than a write speed in the display interval does not cause brings the buffer memory to enter an empty state during a display frame period in the first frame mode; and

the second cycle is a cycle of sufficient length to insure that a successive read action at a speed faster than the write speed in the display interval does not cause brings the buffer memory to enter the empty state during a display frame period in the second frame mode.

8. The panel driver of claim 1, wherein the control circuit is configured to perform, as control for changing the display and non-display intervals in start timing on an individual display frame period basis, control arranged so as to gradually increase, in each display frame period, the first display interval by a predetermined length of time and shorten the last display interval by the predetermined length of time.

9. The panel driver of claim 1, further comprising:

a microprocessor operable to determine a touch or no touch based on signals obtained by the touch controller in during touch detection;

wherein the display controller further comprises;

a start timing register for rewritably holding fifth control data for defining the start timing of the display interval and the start timing of the non-display interval subsequent thereto on an individual display frame period basis for every plurality of display frame periods according to the first frame mode, and the sixth control data for defining the start timing of the display interval on an individual display frame period basis according to the second frame mode; and

wherein the control logic is further configured to select the fifth or sixth control data from the start timing register and provide, based on the selected control data, control signals for the corresponding display and non-display intervals in each display frame period according to the specified display mode; and

wherein the microprocessor specifies the display mode.

10. The panel driver of claim 9, wherein the microprocessor is configured to set the fifth and sixth control data on the start timing register.

11. The panel driver of claim 9, wherein the fifth and sixth control data respectively define the start timing of each of the display and non-display interval by a clock cycle number of the display line clock signal.

12. The panel driver of claim 11, wherein the control logic comprises:

first control logic configured to select required data from among the fifth and sixth control data in each display frame period according to the display mode specified by the microprocessor;

second control logic configured to count the cycle number of the display line clock signal in each display frame period and, in parallel, produce the status signals based on the data selected by the first control logic; and

third control logic configured to receive the status signals and produce display control signals according to the received status signals.

13. The panel driver of claim 1, further comprising a microprocessor operable to determine a touch or no touch based on signals obtained by the touch controller during the non-display interval, wherein:

the microprocessor is configured to notify the display controller of;

a second display mode in which the plurality of display frame periods are handled as one unit subsequently to its reset processing, provided that the second display mode is arranged to;

execute the second frame mode in a portion of the plurality of display frame periods, and

execute the first frame mode in the last display frame period of the plurality of display frame periods;

a first display mode in which the plurality of display frame periods are handled as one unit in the event of detection of a touch after notification of the second display mode, provided that the first display mode is arranged to continue the first frame mode; and

the second display mode in case that a given length of time has elapsed without any a touch being undetected since the notification of the first display mode.

14. The panel driver of claim 13, formed as a semiconductor integrated circuit on a semiconductor substrate.

15. A system, comprising:

a panel having display elements and touch detection electrodes arranged therein;

a panel driver operable to control the panel; and

a host device operable to supply display data to the panel driver,

the panel driver comprising;

a display controller configured to select a display line out of the display elements and provide a display signal to the display line during a display interval;

a touch controller configured to control the touch detection electrodes during a non-display interval,

a microprocessor configured to determine a touch or no touch based on signals obtained by the touch controller during the non-display interval;

wherein the display controller further comprises;

a CPG operable to produce a display line clock signal in synchronization with a display line switching cycle;

a control circuit operable to control first and second frame modes, wherein;

in the first frame mode, the non-display interval and the display interval are alternately generated multiple times during a time interval between opposing blanking intervals of each display frame period, and the touch controller is configured to accept a touch detection directive during the non-display interval;

in the second frame mode, the non-display interval and the display interval subsequent thereto are generated in a time interval between opposing blanking intervals of each display frame period, and the touch controller does not accept a touch detection directive during the non-display interval;

in the first frame mode, the control circuit is further configured to change the display interval and the subsequent non-display interval to start timing on an individual display frame period basis for every plurality of display frame periods;

the CPG is configured to output display line clock signal of a first cycle in the first frame mode, and output a display line clock signal of a second cycle, longer than the first cycle, in the second frame mode;

wherein the control circuit comprises a first control logic configured to count the cycle number of the display line clock signal in each display frame period and, in parallel, sequentially generate status signals when the count value reaches the start timing of each of the display and non-display intervals in the display frame period and output a mode-determination signal indicating whether the status signals are for the first frame mode or the second frame mode; and

wherein the touch controller is further configured to receive the status signals, and generate touch control signals for touch detection according to the received status signals; and

wherein the control circuit further comprises a second control logic, configured to receive the mode-determination signal from the first control logic and, based at least in part on the mode determination signal, supply the CPG with;

a first control signal when the mode-determination signal indicates the first frame mode, and

a second control signal when the mode-determination signal indicates the second frame mode.

16. The system according to claim 15, wherein:

the display controller has a scan line drive circuit operable to output scan line select clock signals for sequentially selecting the scan lines of the display elements, and a signal line drive circuit operable to supply display drive signals to display elements of the selected scan lines;

the scan line drive circuit is configured to change, in pulse, the scan line select clock signals in synchronization with the display line clock signal;

the signal line drive circuit is configured to switch the display drive signals in synchronization with the display line clock signal; and

the scan line drive circuit is configured to output the scan line select clock signals so that a first interval from a timing of output switching of display drive signals to scan line nonselect pulse change of the scan line select clock signals remains unchanged between a case where the cycle of the display line clock signal is the first cycle and a case where the cycle of the display line clock signal is the second cycle.

17. The system according to claim 16, wherein:

the first interval is a difference of a third interval from a second interval;

the scan line drive circuit is configured to change the scan line select clock signals to scan line nonselect pulses when the second interval elapses from the pulse change of the display line clock signal; and

the signal line drive circuit is configured to switch the output of the display drive signals when the third interval elapses from the pulse change of the display line clock signal.

18. The system according to claim 17, wherein:

the display controller has a buffer memory into which display data are written in synchronization with an external horizontal synchronizing signal of a cycle longer than the second cycle, and from which display data are read in synchronization with the display line clock signal;

the first cycle is a cycle of sufficient length to insure that an intermittent read action at a speed faster than a write speed in the display interval does not cause the buffer memory to enter an empty state during a display frame period in the first frame mode; and

the second cycle is a cycle of sufficient length to insure that a successive read action at a speed faster than the write speed in the display interval does not cause the buffer memory to enter the empty state during a display frame period in the second frame mode.

19. The system according to claim 18, further comprising:

a nonvolatile storage in which are rewritably stored;

first control data for specifying the first cycle, second control data for specifying the second cycle, third control data for specifying the second interval, and fourth control data for specifying the third interval; and

wherein the control circuit is further configured to;

rewritably set a clock control register with the first to fourth control data transmitted from the nonvolatile storage, and

issue directions for the first cycle, the second cycle, the second interval and the third interval based on the first to fourth control data.

20. The system according to claim 19, wherein the microprocessor is further configured to respectively set the first to through fourth control data on the clock control register.