Controlling access to previously-stored logic in a reconfigurable logic device
First Claim
1. A system, comprising:
- a computing host comprising one or more processors; and
a single field programmable gate array (FPGA) comprising;
application logic partitions of the FPGA, each of the application logic partitions comprising;
(1) a different one or more of a plurality of reconfigurable logic portions of the FPGA and (2) a different one or more memory devices coupled to the one or more reconfigurable logic portions, each of the memory devices accessible by operation of the respective coupled reconfigurable logic portion,a host logic partition of the FPGA, andan internal configuration circuit of the FPGA configured to erase data stored in a selected one of the application logic partitions,wherein the host logic partition of the FPGA is configured to supervise operations of the internal configuration circuit of the FPGA.
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Accused Products
Abstract
Methods and apparatus are disclosed for securely erasing partitions of reconfigurable logic devices such as FPGAs in a multi-tenant server environment. In one example, a method of securely erasing an FPGA includes identifying one partition of previously-programmed resources in the FPGA, erasing the identified partition by storing new values in memory or storage elements of the identified partition, and storing new values in memory or storage elements of additional external resources electrically connected to the integrated circuit and associated with the identified partition. Thus, other partitions and subsequent users of the identified partition are prevented from accessing the securely erased data. A configuration circuit, accessible by a host computer via DMA, can be programmed into the FPGA reconfigurable logic for performing the disclosed erasing operations.
89 Citations
18 Claims
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1. A system, comprising:
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a computing host comprising one or more processors; and a single field programmable gate array (FPGA) comprising; application logic partitions of the FPGA, each of the application logic partitions comprising;
(1) a different one or more of a plurality of reconfigurable logic portions of the FPGA and (2) a different one or more memory devices coupled to the one or more reconfigurable logic portions, each of the memory devices accessible by operation of the respective coupled reconfigurable logic portion,a host logic partition of the FPGA, and an internal configuration circuit of the FPGA configured to erase data stored in a selected one of the application logic partitions, wherein the host logic partition of the FPGA is configured to supervise operations of the internal configuration circuit of the FPGA. - View Dependent Claims (2, 3, 4)
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5. A system, comprising:
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a server computer comprising one or more processors; a reconfigurable logic device coupled to the server computer, the reconfigurable logic device having logic partitioned into a plurality of user logic partitions and a host logic partition, each of the user logic partitions being controlled by a different process executing on the server computer to perform a logic function; and a reconfiguration circuit of the reconfigurable logic device configured to erase data from a selected one of the user logic partitions by overwriting values in memory and storage and clearing logic configurations of the selected user logic partition, wherein the host logic partition is configured to supervise operations of the reconfiguration circuit. - View Dependent Claims (6, 7, 8, 9, 10)
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11. A method, comprising:
with a reconfiguration circuit coupled to a reconfigurable logic device having logic partitioned into a plurality of user logic partitions to perform logic functions by hardware resources of the reconfigurable logic device based on values stored in memory and storage within or associated with the reconfigurable logic device; erasing data from a selected one of the user logic partitions of the reconfigurable logic device by overwriting values in memory and storage within or associated with the selected user logic partition and by clearing logic configurations of the selected user logic partition, wherein each of the user logic partitions is controlled by a different process executing on a server computer coupled to the reconfigurable logic device. - View Dependent Claims (12)
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13. A system, comprising:
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a server computer comprising one or more processors; a reconfigurable logic device coupled to the server computer, the reconfigurable logic device having logic partitioned into a plurality of user logic partitions and a host logic partition, each of the user logic partitions being controlled by a different process executing on the server computer to perform a logic function; and a reconfiguration circuit coupled to the reconfigurable logic device, the reconfiguration circuit configured to erase data from a selected one of the user logic partitions, wherein the reconfiguration circuit is coupled to the server computer with a direct memory access (DMA) connection, wherein the host logic partition is configured to supervise operations of the reconfiguration circuit. - View Dependent Claims (14, 15, 16, 17, 18)
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Specification