System, method and computer program product for instantiating blocks of a solid-state disk to include different flash characteristics

• US 10,642,497 B2
• Filed: 08/31/2016
• Issued: 05/05/2020
• Est. Priority Date: 08/31/2016
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Maghraoui, Kaoutar El, Franke, Hubertus, Hunter, Hillery C., Kandiraju, Gokul Bhargava, Penner, Hartmut Erhard
• Primary Examiner(s): Dudek, Jr., Edward J
• Assistant Examiner(s): Russell, Andrew
• Application Number:
  US15/252,328
• Publication Number:
  US 20180059932A1
• Time in Patent Office: 1,343 Days
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

A flash translation layer method, system, and computer program product, include sending a request with a type of feature and a flash characteristic of a translation table for a Solid-State disk, receiving, via a meta-flash translation layer (meta-FTL), the request and checking for a number of free blocks in a NAND chip, and instantiating a range in the NAND chip including the number of free blocks using the meta-FTL to create a compatible range of blocks for the type of feature and the flash characteristic of the translation table if the checking returns a confirmation that the number of free blocks is available.

Claims

1. A computer-implemented flash translation layer method, the method comprising:

sending a request with a type of feature and a flash characteristic of a translation table for a Solid-State disk;

receiving, via a meta-flash translation layer (meta-FTL), the request and checking for a number of free blocks in a NAND chip;

performing a virtualization of the meta-flash translation layer by;

instantiating a range in the NAND chip comprising the number of free blocks using the meta-FTL to create a compatible range of blocks for the type of feature and the flash characteristic of the translation table if the checking returns a confirmation that the number of free blocks is available; and

instantiating a second range in the NAND chip comprising a second number of free blocks using the meta-FTL to create a second compatible range of blocks for a second type of feature and a second flash characteristic of the translation table; and

dynamically programming data on the fly based on an input requirement of the request into the range and the second range,

wherein the type of feature comprises a first type of feature,

wherein the second type of feature comprises a different feature than the first type of feature, and

wherein the meta-flash translation layer comprises a plurality of data structures.

2. The computer-implemented method of claim 1, further comprising allocating the instantiated range in the NAND chip for an operation request of an operating system.

3. The computer-implemented method of claim 2, wherein the allocating allocates the instantiated range using pre-programed software code for the operation request of the type of feature.

4. The computer-implemented method of claim 1, wherein the instantiating creates the instantiated range in the NAND chip as a partitioned segment of a total number of blocks of the NAND chip.

5. The computer-implemented method of claim 4, wherein the second range comprises a second partitioned segment of the total number of blocks of the NAND chip.

6. The computer-implemented method of claim 5, wherein the partitioned segment and the second partitioned segment comprise a different type of flash characteristic.

7. The computer-implemented method of claim 1, wherein the flash characteristic of the translation table comprises a format for a mapping function of the NAND chip.

8. The computer-implemented method of claim 1, implemented in a cloud-computing environment.

9. The computer-implemented method of claim 1, wherein the second type and the first type comprise a different type of flash characteristic of the translation table.

10. The computer-implemented method of claim 1, wherein the first range in the NAND chip and the second range in the NAND chip are allocated for a request from an operating system.

11. The computer-implemented method of claim 1, wherein the first range in the NAND chip and the second range in the NAND chip are allocated for a different function performed by an operating system.

12. The computer-implemented method of claim 1, wherein the type of feature and the second type of feature are based on a desired type of function for the range and the second range in the NAND chip.

13. The computer-implemented method of claim 1, further comprising instantiating a third range in the NAND chip comprising a third number of free blocks using the meta-FTL to create a third compatible range of blocks for a third type of feature and a third flash characteristic of the translation table,

wherein the flash characteristic and the second flash characteristic include a same flash characteristic, and

wherein the second flash characteristic and the third flash characteristic include a different flash characteristic.

14. A computer program product for a flash translation layer of a Solid-State disk, the computer program product comprising a computer-readable storage medium having program instructions embodied therewith, the program instructions executable by a computer to cause the computer to perform:

sending a request with a type of feature and a flash characteristic of a translation table for the Solid-State disk;

receiving, via a meta-flash translation layer (meta-FTL), the request and checking for a number of free blocks in a NAND chip;

performing a virtualization of the meta-flash translation layer by;

instantiating a range in the NAND chip comprising the number of free blocks using the meta-FTL to create a compatible range of blocks for the type of feature and the flash characteristic of the translation table if the checking returns a confirmation that the number of free blocks is available; and

instantiating a second range in the NAND chip comprising a second number of free blocks using the meta-FTL to create a second compatible range of blocks for a second type of feature and a second flash characteristic of the translation table; and

dynamically programming data on the fly based on an input requirement of the request into the range and the second range,

wherein the type of feature comprises a first type of feature,

wherein the second type of feature comprises a different feature than the first type of feature, and

wherein the meta-flash translation layer comprises a plurality of data structures.

15. The computer-program product of claim 14, further comprising allocating the instantiated range in the NAND chip for an operation request of an operating system.

16. The computer-program product of claim 15, wherein the allocating allocates the instantiated range using pre-programed software code for the operation request of the type of feature.

17. The computer-program product of claim 14, wherein the instantiating creates the instantiated range in the NAND chip as a partitioned segment of a total number of blocks of the NAND chip.

18. The computer-program product of claim 17, wherein the second range comprises a second partitioned segment of the total number of blocks of the NAND chip.

19. A flash translation layer system, said system comprising:

a processor; and

a memory, the memory storing instructions to cause the processor to;

send a request with a type of feature and a flash characteristic of a translation table for a Solid-State disk;

receive, via a meta-flash translation layer (meta-FTL) the request and checking for a number of free blocks in a NAND chip;

performing a virtualization of the meta-flash translation layer by;

instantiating a range in the NAND chip comprising the number of free blocks using the meta-FTL to create a compatible range of blocks for the type of feature and the flash characteristic of the translation table if the checking returns a confirmation that the number of free blocks is available; and

instantiating a second range in the NAND chip comprising a second number of free blocks using the meta-FTL to create a second compatible range of blocks for a second type of feature and a second flash characteristic of the translation table; and

dynamically program data on the fly based on an input requirement of the request into the range and the second range,

wherein the type of feature comprises a first type of feature,

wherein the second type of feature comprises a different feature than the first type of feature, and

wherein the meta-flash translation layer comprises a plurality of data structures.

20. The system of claim 19, implemented in a cloud-computing environment.