Extensible storage system and method

• US 10,642,503 B2
• Filed: 06/25/2019
• Issued: 05/05/2020
• Est. Priority Date: 07/29/2016
• Status: Active Grant

• Current Assignee: JP Morgan Chase Bank, N.A. (JP Morgan Chase & Co)
• Original Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Inventors: Koul, Rajesh, Mullendore, Rodney N., Walsh, James J.
• Primary Examiner(s): Cleary, Thomas J.
• Application Number:
  US16/452,465
• Publication Number:
  US 20190310779A1
• Time in Patent Office: 315 Days
• CPC Class Codes: G06F 13/102 where the programme performs an interfacing function, e.g. device driver G06F13/105 takes precedence; scheduling within device drivers G06F9/52; contention policies within device drivers G06F9/4881
• CPC Class Codes: G06F 13/4045 where the bus bridge performs an extender function
• CPC Class Codes: G06F 3/0607 by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0664 at device level, e.g. emulation of a storage device or system
• CPC Class Codes: G06F 3/0683 Plurality of storage devices
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A storage system controller chip includes routing circuitry comprising a host interface for coupling to a host device and an extension interface for coupling to a secondary controller chip. A host controller is coupled to a logical interface of the routing circuitry for receiving a host data access command from the host device via the host interface and logical interface. The routing circuitry transfers the host data access command to the secondary controller chip via the extension interface. The storage system controller chip further includes processor circuitry coupled to the logical interface of the routing circuitry. The processor circuitry receives an indication from the secondary controller chip via the extension interface that execution of the host data access command has been completed by the secondary controller chip and instructs the host controller to notify the host device that execution of the host data access command has been completed.

Claims

1. A data storage system comprising:

a primary controller chip comprising a first host interface and a first extension interface, the first host interface configured to be coupled to a host device; and

a secondary controller chip coupled to the first extension interface,

wherein the secondary controller chip is one of one or more secondary controller chips, a bandwidth of the first host interface is greater than a bandwidth of the first extension interface, the bandwidth of the first host interface is split among the primary controller chip and the one or more secondary controller chips, and each of the primary controller chip and the secondary controller chip is configured to utilize less than an entirety of the bandwidth of the first host interface, and

wherein the primary controller chip is configured to;

receive a host data access command from the host device via the first host interface;

transfer the host data access command to the secondary controller chip; and

provide a notification that execution of the host data access command has been completed.

2. The data storage system of claim 1, wherein the primary controller chip is configured to:

process the host data access command to identify data referenced in the host data access command;

determine that at least a first portion of the referenced data is associated with the primary controller chip and a first storage media of the primary controller chip;

execute the host data access command for the first portion of the referenced data in the first storage media;

determine that a second portion of the referenced data is associated with the secondary controller chip and a second storage media of the secondary controller chip;

transfer the host data access command to the secondary controller chip in response to determining that the second portion of the reference data is associated with the secondary controller chip; and

provide the notification to the host device that the execution of the host data access command has been completed in response to receiving an indication from the secondary controller chip that execution of the transferred host data access command by the secondary controller chip has been completed and in response to the primary controller chip completing execution of the host data access command.

3. The data storage system of claim 2, wherein the primary controller chip is configured to:

determine logical addressing of the data referenced in the host data access command; and

compare the determined logical addressing to a logical address range associated with the secondary controller chip and the second storage media,

wherein the logical addressing of the second portion of the referenced data falls within the logical address range associated with the secondary controller chip and the second storage media.

4. The data storage system of claim 3, wherein the primary controller chip is configured to:

modify the host data access command based on the logical address range associated with the secondary controller chip and the second storage media; and

transfer the modified host data access command to the secondary controller chip.

5. The data storage system of claim 2, wherein the primary controller chip is configured to:

determine a logical namespace of the data referenced in the host data access command; and

compare the determined logical namespace with a logical namespace associated with the secondary controller chip and the second storage media.

6. The data storage system of claim 1, wherein the primary controller chip comprises a switch having ports corresponding to the first host interface and the first extension interface.

7. The data storage system of claim 1, wherein the primary controller chip comprises a first logical interface configured to receive the host data access command or a second host data access command for execution in the primary controller chip, and wherein the bandwidth of the first host interface is equal to or greater than a sum of a bandwidth of the first logical interface and the bandwidth of the first extension interface.

8. The data storage system of claim 1, wherein the primary controller chip comprises a respective host controller, the respective host controller comprising a direct memory access (DMA) module, a host command fetch module and a host command complete module,

wherein the DMA module is configured to transfer data between the host device and components within the primary controller chip,

wherein the host command fetch module is configured to fetch a respective host data access command from the host device upon receiving an indication that the respective host data access command is ready for processing, and

wherein the host command complete module is configured to, in response to all portions of the respective host data access command being completed, notify the host device that the respective host data access command has been completed.

9. The data storage system of claim 1, wherein the first host interface and the first extension interface comprise respective PCIe interfaces, the bandwidth of the first host interface corresponds to a particular bandwidth associated with PCIe x32 and the bandwidth of the first extension interface corresponds to a particular bandwidth associated with PCIe x4, and an amount of available bandwidth supports eight respective controller chips and associated storage media based at least in part on a ratio of the particular bandwidth associated with PCIe x32 and the particular bandwidth associated with PCIe x4.

10. A machine-implemented method, comprising:

receiving a host data access command at a primary controller chip coupled to a host device via a host interface of the primary controller chip;

transferring the host data access command from the primary controller chip to a secondary controller chip coupled to the primary controller chip via an extension interface of the primary controller chip, wherein the secondary controller chip is one of one or more secondary controller chips, a bandwidth of the host interface is greater than a bandwidth of the extension interface, the bandwidth of the host interface is split among the primary controller chip and the one or more secondary controller chips, and each of the primary controller chip and the secondary controller chip utilizes less than an entirety of the bandwidth of the host interface; and

providing a notification that execution of the host data access command has been completed.

11. The machine-implemented method of claim 10, further comprising:

receiving an indication from the secondary controller chip that execution of the transferred host data access command by the secondary controller chip has been completed,

wherein the notification is provided to the host device in response to the received indication.

12. The machine-implemented method of claim 11, further comprising:

processing the host data access command at the primary controller chip to identify data referenced in the host data access command;

determining that the primary controller chip is responsible for a first portion of the data referenced in the host data access command;

determining that the secondary controller chip is responsible for a second portion of the data referenced in the host data access command, wherein the host data access command is transferred to the secondary controller chip in response to determining the secondary controller chip is responsible for the second portion of the data referenced in the host data access command; and

executing the host data access command by the primary controller chip for the first portion of the data,

wherein the notification is provided to the host device further in response to the primary controller chip completing execution of the host data access command for the first portion of the data.

13. The machine-implemented method of claim 12, wherein determining the secondary controller chip responsible for the second portion of the data comprises:

determining logical addressing of the data referenced in the host data access command; and

comparing the logical addressing to a logical address range associated with the secondary controller chip,

wherein logical addressing of the second portion of the data falls within the logical address range associated with the secondary controller chip.

14. The machine-implemented method of claim 13, further comprising:

modifying the host data access command based on the logical address range associated with the secondary controller chip,

wherein the modified host data access command is transferred to the secondary controller chip.

15. The machine-implemented method of claim 12, wherein determining the secondary controller chip responsible for the second portion of the data comprises:

determining a logical namespace of the data referenced in the host data access command; and

comparing the logical namespace of the referenced data with a logical namespace associated with the secondary controller chip,

wherein the logical namespace of the second portion of the data matches the logical namespace associated with the secondary controller chip.

16. The machine-implemented method of claim 12, further comprising:

receiving the host data access command at the secondary controller chip coupled to the primary controller chip via a host interface of the secondary controller chip;

executing the host data access command by the secondary controller chip for the second portion of the data; and

notifying the primary controller chip that the host data access command has been completed for the second portion of the data.

17. The machine-implemented method of claim 10, the primary controller chip comprises a logical interface which receives the host data access command or a second host data access command for execution, and wherein the bandwidth of the host interface is equal to or greater than a sum of a bandwidth of the logical interface and the bandwidth of the extension interface.

18. An apparatus, comprising:

means for receiving a host data access command at a primary controller chip coupled to a host device via a host interface of the primary controller chip;

means for transferring the host data access command from the primary controller chip to a secondary controller chip coupled to the primary controller chip via an extension interface of the primary controller chip, wherein the secondary controller chip is one of one or more secondary controller chips, a bandwidth of the host interface is greater than a bandwidth of the extension interface, the bandwidth of the host interface is split among the primary controller chip and the one or more secondary controller chips, and each of the primary controller chip and the secondary controller chip utilizes less than an entirety of the bandwidth of the host interface; and

means for providing a notification that execution of the host data access command has been completed.

19. The apparatus of claim 18, further comprising:

means for receiving an indication from the secondary controller chip that execution of the transferred host data access command by the secondary controller chip has been completed,

wherein the means for providing the notification comprises means for providing the notification to the host device in response to the received indication.

20. The apparatus of claim 19, further comprising:

means for processing the host data access command at the primary controller chip to identify data referenced in the host data access command;

means for determining that the primary controller chip is responsible for a first portion of the data referenced in the host data access command;

means for determining that the secondary controller chip is responsible for a second portion of the data referenced in the host data access command;

means for transferring the host data access command to the secondary controller chip in response to determining the secondary controller chip is responsible for the second portion of the data referenced in the host data access command; and

means for executing the host data access command by the primary controller chip for the first portion of the data,

wherein the means for providing the notification to the host device comprises means for providing the notification to the host device in response to the primary controller chip completing execution of the host data access command for the first portion of the data.