Techniques for data migration based on per-data metrics and memory degradation

• US 10,642,505 B1
• Filed: 09/08/2015
• Issued: 05/05/2020
• Est. Priority Date: 01/28/2013
• Status: Active Grant

• Current Assignee: Radian Memory Systems, Inc.
• Original Assignee: Radian Memory Systems, Inc.
• Inventors: Kuzmin, Andrey V., Chen, Alan, Lercari, Robert
• Primary Examiner(s): Yi, David
• Assistant Examiner(s): Ahmed, Zubair
• Application Number:
  US14/848,273
• Time in Patent Office: 1,701 Days
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G06F 3/0605 by facilitating the interaction with a user or administrator
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/0647 Migration mechanisms
• CPC Class Codes: G06F 3/0649 Lifecycle management
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0685 Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays

Abstract

This disclosure provides techniques for managing memory which match per-data metrics to those of other data or to memory destination. In one embodiment, wear data is tracked for at least one tier of nonvolatile memory (e.g., flash memory) and a measure of data persistence (e.g., age, write frequency, etc.) is generated or tracked for each data item. Memory wear management based on these individually-generated or tracked metrics is enhanced by storing or migrating data in a manner where persistent data is stored in relatively worn memory locations (e.g., relatively more-worn flash memory) while temporary data is stored in memory that is less worn or is less susceptible to wear. Other data placement or migration techniques are also disclosed.

Claims

1. A memory controller integrated circuit to control nonvolatile memory, comprising:

an interface to receive commands from a host;

logic to update metadata values for respective logical addresses corresponding to data stored in the nonvolatile memory in response to data access operations commanded by the host, to identify a subset of the one or more of the metadata values which meet at least one criterion and, in response to identification of the one or more metadata values which meet the at least one criterion, to transmit to the host a notification; and

logic to maintain wear information associated with independently erasable units of physical memory locations in the nonvolatile memory, and to identify at least one of the independently erasable units dependent on the respective wear information as a candidate relocation target destination in which to relocate data within the nonvolatile memory which corresponds to a specific logical address to a different physical storage location, the data corresponding to the specific logical address selected dependent on the subset;

wherein each metadata value represents at least one of prior read of data associated with a corresponding one of the logical addresses, frequency of read of the data associated with the corresponding one of the logical addresses, age since last write of the data associated with the corresponding one of the logical addresses, or frequency of write of the data associated with the corresponding one of the logical addresses;

wherein the memory controller integrated circuit is to receive a command from the host to move the data corresponding to the specific logical address in response to the notification to the host; and

wherein the memory controller integrated circuit comprises logic to execute the move of the data corresponding to the specific logical address to the candidate relocation target destination in response to the command to move.

2. The memory controller integrated circuit of claim 1, wherein each metadata value comprises a time stamp that identifies when data corresponding to a respective logical address was last modified.

3. The memory controller integrated circuit of claim 1, wherein:

the memory controller integrated circuit comprises a memory controller for flash memory and the nonvolatile memory is flash memory;

said memory controller integrated circuit is further to transmit to the host address information associated with the at least one of the independently erasable units identified as the candidate relocation target destination;

the command to move is to specify a destination address for the movement of the data corresponding to the specific logical address, the specified destination address dependent on the address information sent to the host; and

the logic to execute the move is responsive to the command to move to move the data corresponding to the specific logical address to the specified destination address.

4. The memory controller integrated circuit of claim 3, wherein said memory controller integrated circuit is to move the data corresponding to the specific logical address to the specified destination address without transmitting the data corresponding to the specific logical address to the host.

5. The memory controller integrated circuit of claim 1, wherein the nonvolatile memory comprises a shingle drive memory and wherein said memory controller integrated circuit is adapted to control the shingle drive memory.

6. The memory controller integrated circuit of claim 1, wherein the nonvolatile memory is flash memory, wherein said commands include read commands and write commands, wherein said read commands and said write commands are to specify first addresses, and wherein said memory controller integrated circuit is to responsively transmit to the flash memory corresponding read commands and write commands that specify addresses which preserve an address offset relative to a boundary of a first physical structure in the flash memory, the address offset also specified by the first addresses, the address offset corresponding to a second physical structure in the flash memory.

10. The memory controller integrated circuit of claim 1, wherein the notification comprises address information for each of one or more of the respective logical addresses corresponding to the specific logical address.

11. The memory controller integrated circuit of claim 10, wherein the data corresponding to the specific logical address comprises content of the one or more of the respective logical addresses for which the metadata values meet the at least one criterion, and wherein the command to move from the host is to explicitly specify at least one source address for the data corresponding to the specific logical address which is to be moved to the candidate relocation target destination.

12. The memory controller integrated circuit of claim 1, wherein the command to move comprises an address that explicitly designates the candidate relocation target destination, and wherein the logic to execute the move is to move the data corresponding to the specific logical address to the address explicitly designated by the command to move from the host.

13. The memory controller integrated circuit of claim 1, wherein:

the logic to maintain and to identify is to identify at least two alternative candidate relocation target destinations dependent on comparison of the maintained wear information and at least one second criterion;

the memory controller integrated circuit is to transmit identification of each of the at least two alternative candidate relocation destinations to the host; and

the command to move received from the host is to specify a host-selected-one of the at least two alternative candidate relocation destinations, such that the host is to select a move destination from among the alternative candidate relocation target destinations and the memory controller is to move the data corresponding to the specific logical address to the host-selected move destination.

14. The memory controller integrated circuit of claim 1, wherein:

the logic to maintain and to identify is to identify at least two alternative candidate relocation target destinations dependent on comparison of the maintained wear information and at least one second criterion;

the memory controller integrated circuit is to select between the at least two alternative candidate relocation destinations; and

in response to the command to move received from the host, the memory controller is to move the data corresponding to the specific logical address to the memory controller-selected move destination.

15. The memory controller integrated circuit of claim 1, wherein:

the memory controller integrated circuit comprises a memory controller for flash memory and the nonvolatile memory is flash memory;

the metadata values each comprise an age since write metric associated with the respective logical address;

the at least one criterion comprises an age since write criterion, such that the subset represents one or more of the logical addresses which satisfy the age since write criterion;

the logic to maintain and identify is to perform one of

(a) identification of one or more independently erasable units of the non-volatile memory as relatively worn, or

(b) identification of one or more independently erasable units of the non-volatile memory as relatively unworn;

the move command is to cause the memory controller integrated circuit to transfer data from a source location in the nonvolatile memory selected dependent on the age since write criterion to a destination location selected dependent on wear of the destination location relative to others of the independently erasable units.

16. The memory controller integrated circuit of claim 1, wherein:

the memory controller integrated circuit comprises a memory controller for flash memory and the nonvolatile memory is flash memory;

the metadata values each comprise a frequency of read metric associated with the respective logical address;

the at least one criterion comprises a frequency of read criterion, such that the subset represents one or more of the logical addresses which satisfy the frequency of read criterion;

the logic to maintain and identify is to perform one of

(a) identification of one or more independently erasable units of the non-volatile memory as relatively worn, or

(b) identification of one or more independently erasable units of the non-volatile memory as relatively unworn;

the move command is to cause the memory controller integrated circuit to transfer data from a source location in the nonvolatile memory selected dependent on the frequency of read criterion to a destination location selected dependent on wear of the destination location relative to others of the independently erasable units.

27. The memory controller integrated circuit of claim 1, wherein in response to the command to move, the logic to execute the move is to move only the data corresponding to the specific logical address, and is not to move other data stored in the nonvolatile memory where said other data is not associated with the specific logical address.

28. The memory controller integrated circuit of claim 1, wherein said memory controller integrated circuit further comprises address translation logic to translate each logical address specified by the host to an address for one of the physical memory locations in the nonvolatile memory.

7. A memory controller integrated circuit to control flash memory, comprising:

an interface to receive commands from a host;

logic to update metadata values for respective pages of data stored in the flash memory in response to data access operations commanded by the host, each page of data being associated with a respective logical address, to identify one or more of the pages of data corresponding to a subset of the metadata values which meet at least one criterion and, in response to identification of the one or more of the respective pages of data, to transmit to the host a notification; and

logic to maintain wear information associated with independent erase units (EUs) of the flash memory, each EU representing physical storage locations within the flash memory, and to identify at least one of the EUs dependent on the respective wear information as a candidate relocation target destination in which to relocate data within the flash memory which corresponds to a specific logical address, the data corresponding to the specific logical address selected dependent on the subset;

wherein each metadata value represents at least one of prior read of a corresponding one of the respective pages of data, frequency of read of the corresponding one of the respective pages of data, age since last write of the corresponding one of the respective pages of data, or frequency of write of the corresponding one of the respective pages of data;

wherein the memory controller integrated circuit is to receive a command from the host to move data corresponding to the specific logical address in response to the notification to the host; and

wherein the memory controller integrated circuit comprises logic to execute the move of the data corresponding to the specific logical address to the candidate relocation target destination in response to the command to move.

8. The memory controller integrated circuit of claim 7, wherein each metadata value comprises a time stamp that identifies when data stored at a corresponding one of the respective logical page addresses was last modified.

9. The memory controller integrated circuit of claim 7, wherein said commands include read commands and write commands, wherein said read commands and said write commands are to specify first logical addresses in the flash memory, and wherein said memory controller integrated circuit is to responsively transmit corresponding read commands and write commands to the flash memory which preserve an address offset relative to a boundary of a first physical structure in the flash memory, the address offset also specified by the first addresses, the address offset corresponding to a second physical structure in the flash memory.

17. The memory controller integrated circuit of claim 7, wherein the notification comprises address information for each of one or more of the respective pages of data corresponding to the specific logical address.

18. The memory controller integrated circuit of claim 17, wherein the data corresponding to the specific logical address comprises content of the one or more of the respective pages of data for which the metadata values meet the criterion, and wherein the command to move from the host is to explicitly specify at least one source address for the data corresponding to the specific logical address which is to be moved to the candidate relocation target destination.

19. The memory controller integrated circuit of claim 7, wherein the command to move comprises an address that explicitly designates the candidate relocation target destination, and wherein the logic to execute the move is to the data corresponding to the specific logical address to the address explicitly designated by the command to move from the host.

20. The memory controller integrated circuit of claim 7, wherein:

the logic to maintain and to identify is to identify at least two alternative candidate relocation target destinations dependent on comparison of the maintained wear information and at least one second criterion;

the memory controller integrated circuit is to transmit identification of each of the at least two alternative candidate relocation destinations to the host; and

the command to move received from the host is to specify a host-selected-one of the at least two alternative candidate relocation destinations, such that the host is to select a move destination from among the alternative candidate relocation target destinations and the memory controller is to move the data corresponding to the specific logical address to the host-selected move destination.

21. The memory controller integrated circuit of claim 7, wherein:

the logic to maintain and to identify is to identify at least two alternative candidate relocation target destinations dependent on comparison of the maintained wear information and at least one second criterion;

the memory controller integrated circuit is to select between the at least two alternative candidate relocation destinations; and

in response to the command to move received from the host, the memory controller is to move the data corresponding to the specific logical address to the memory controller-selected move destination.

22. The memory controller integrated circuit of claim 7, wherein:

the metadata values each comprise an age since write metric associated with the respective page of data;

the at least one criterion comprises an age since write criterion, such that the subset represents one or more of the respective pages of data in the flash memory which satisfy the age since write criterion;

the logic to maintain and identify is to perform one of

(a) identification of one or more of the EUs as relatively worn, or

(b) identification of one or more of the EUs as relatively unworn;

the move command is to cause the memory controller integrated circuit to transfer one or more pages of data from a source physical storage location in the flash memory selected dependent on the age since write criterion to a physical destination location selected dependent on wear of the destination location relative to others of the EUs in the flash memory.

23. The memory controller integrated circuit of claim 7, wherein:

the metadata values each comprise a frequency of read metric associated with the respective page of data;

the at least one criterion comprises a frequency of read criterion, such that the subset represents one or more of the respective pages of data in the flash memory which satisfy the frequency of read criterion;

the logic to maintain and identify is to perform one of

(a) identification of one or more of the EUs as relatively worn, or

(b) identification of one or more of the EUs as relatively unworn;

the move command is to cause the memory controller integrated circuit to transfer one or more pages of data from a source physical storage location in the nonvolatile memory selected dependent on the frequency of read criterion to a physical destination location selected dependent on wear of the destination location relative to others of the EUs in the flash memory.

24. The memory controller integrated circuit of claim 7, wherein:

said memory controller integrated circuit is further to transmit to the host address information associated with the at least one of the EUs identified as the candidate relocation target destination;

the command to move is to specify a destination address for the movement of the data corresponding to the specific logical address, the specified destination address dependent on the address information sent to the host; and

the logic to execute the move is responsive to the command to move to move the data corresponding to the specific logical address to the specified destination address.

25. The memory controller integrated circuit of claim 24, wherein said memory controller integrated circuit is to move the data corresponding to the specific logical address to the specified destination address without transmitting the data corresponding to the specific logical address to the host.

29. The memory controller integrated circuit of claim 7, wherein in response to the command to move, the logic to execute the move is to move only the data corresponding to the specific logical address, and is not to move other data stored in the nonvolatile memory where said other data is not associated with the specific logical address.

30. The memory controller integrated circuit of claim 7, wherein said memory controller integrated circuit further comprises address translation logic to translate each logical address specified by the host to an address for one of the physical memory locations in the nonvolatile memory.

26. A storage drive, comprising:

flash memory;

a memory controller integrated circuit to control the flash memory, the memory controller integrated circuit comprising

an interface to receive commands from a host,

logic to update metadata values for respective pages of data stored in the flash memory in response to data access operations commanded by the host, each of the pages of data corresponding to a respective logical address, to identify one or more of the pages of data corresponding to a subset of the metadata values which meet at least one criterion and, in response to identification of the one or more of the respective pages of data, to transmit to the host a notification, and

logic to maintain wear information associated with independent erase units (EUs) of the flash memory, each EU representing physical storage locations in said flash memory, and to identify at least one of the EUs dependent on the respective wear information as a candidate relocation target destination in which to relocate data corresponding to a specific logical address, the data corresponding to the specific logical address selected dependent on the subset,

wherein each metadata value represents at least one of prior read of a corresponding one of the respective pages of data, frequency of read of the corresponding one of the pages of data, age since last write of the corresponding one of the respective pages of data, or frequency of write of the corresponding one of the pages of data,

wherein the memory controller integrated circuit is to receive a command from the host to move the data corresponding to the specific logical address in response to the notification to the host, and

wherein the memory controller integrated circuit comprises logic to execute the move of the data corresponding to the specific logical address to the candidate relocation target destination in response to the command to move.

31. The storage drive of claim 26, wherein in response to the command to move, the logic to execute the move is to move only the data corresponding to the specific logical address, and is not to move other data stored in the nonvolatile memory where said other data is not associated with the specific logical address.

32. The storage drive of claim 26, wherein said memory controller integrated circuit further comprises address translation logic to translate each logical address specified by the host to an address for one of the physical memory locations in the nonvolatile memory.