Low-speed memory operation
First Claim
1. A method, comprising:
- identifying a clock mode for a system clock that generates a system clock signal, wherein a first memory die and a second memory die are each configured to receive the system clock signal and a common data clock signal;
generating an internal data clock signal for the first memory die; and
routing the internal data clock signal to a data clock tree of the first memory die based at least in part on identifying the clock mode.
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Abstract
Methods, systems, and devices for a low-speed memory operation are described. A controller associated with a memory device may, for example, identify a clock mode for a system clock and determine that a speed of the system clock is below a threshold. The controller may generate (or cause to be generated) an internal data clock signal having a shorter period than an external data clock signal (which may have a speed based on the system clock speed). Also, the controller may use, instead of the external data clock signal, the internal data clock signal to generate data from the memory device, which may provide reduced latency. Further, the controller may deactivate (or cause to be deactivated) an external data clock that generates the external data clock signal.
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Citations
35 Claims
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1. A method, comprising:
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identifying a clock mode for a system clock that generates a system clock signal, wherein a first memory die and a second memory die are each configured to receive the system clock signal and a common data clock signal; generating an internal data clock signal for the first memory die; and routing the internal data clock signal to a data clock tree of the first memory die based at least in part on identifying the clock mode. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A method, comprising:
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identifying a system clock speed as below a threshold, the system clock speed being associated with a system clock signal that is common to a first memory die and a second memory die; disconnecting a common data clock from a data clock tree of the first memory die based at least in part on identifying the system clock speed as below the threshold, the common data clock generating a common data clock signal that is common to the first memory die and the second memory die; and connecting an internal data clock within the first memory die to the data clock tree based at least in part on identifying the system clock speed as below the threshold. - View Dependent Claims (15, 16, 17, 18, 19)
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20. An apparatus, comprising:
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a first memory die configured to receive a common data clock signal that is common to the first memory die and a second memory die; an internal data clock included in the first memory die and configured to generate an internal data clock signal for the first memory die; and a selection component configured to route the common data clock signal or the internal data clock signal to a data clock tree of the first memory die based at least in part on a mode of operation of the first memory die. - View Dependent Claims (21, 22, 23, 24, 25, 26, 27)
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28. An apparatus, comprising:
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a first memory die configured to receive a system clock signal and a common data clock signal; a second memory die configured to receive the system clock signal and the common data clock signal; an internal data clock included in the first memory die and configured to generate an internal data clock signal for the first memory die, wherein the internal data clock signal has a first period and the common data clock signal has a second period that is longer than the first period; and a selection component included in the first memory die, the selection component configured to select the common data clock signal or the internal data clock signal based at least in part on a speed of the system clock signal. - View Dependent Claims (29, 30, 31)
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32. An apparatus, comprising:
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a first memory die configured to receive a system clock signal and a common data clock signal; a second memory die configured to receive the system clock signal and the common data clock signal; and a controller configured to; set a speed of the system clock signal to a first speed, wherein the system clock signal supports the first speed and a second speed greater than the first speed; and disable the common data clock signal based at least in part on setting the speed of the system clock signal to the first speed. - View Dependent Claims (33, 34, 35)
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Specification