Register access in a distributed memory buffer system

• US 10,642,535 B2
• Filed: 01/23/2018
• Issued: 05/05/2020
• Est. Priority Date: 01/23/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Carlough, Steven R., Cebulla, Markus, Eickhoff, Susan M., Friedman, Logan I., Meaney, Patrick J., Pietschmann, Walter, Rolfe, Nicholas, Van Huben, Gary A.
• Primary Examiner(s): Alrobaie, Khamdan N.
• Application Number:
  US15/877,661
• Publication Number:
  US 20190227741A1
• Time in Patent Office: 833 Days
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/068 Hybrid storage device
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits

Abstract

A memory system, architecture, and method for storing data in response to commands received from a host is disclosed. The memory system includes a memory control circuit configured to receive commands from the host; at least one memory device configured to store data; and at least one data buffer circuit associated with the at least one memory device and the memory control circuit, the data buffer circuit having data buffers and at least one register. The system preferably includes communication links between the host, the at least one memory control circuit, the at least one data buffer circuit, and the at least one memory device. The system preferably is configured so that register access commands are sent by the host to the memory control circuit over the communication links between the host and the memory control circuit.

Claims

1. A memory system for storing data in response to a command received from a host, the memory system comprising:

a memory control circuit having a scheduler and at least one register, the memory control circuit configured to receive commands from the host and to output command and control signals;

at least one memory device configured to store data;

at least one data buffer circuit associated with the at least one memory device and the memory control circuit, the data buffer circuit having data buffers and at least one register associated therewith;

a communications link for communicating between the host and the at least one memory control circuit;

a first data communications link between the host and the at least one data buffer circuit, and a second data communications link between the at least one data buffer circuit and the at least one memory device; and

a control communications link between the memory control circuit and the at least one data buffer circuit,

wherein the system is configured so that register access commands are sent by the host to the memory control circuit over the communications link between the host and the memory control circuit, and

wherein the system comprises a plurality of data buffer circuits configured as at least one of a rank, a channel, or both, wherein the memory control circuit is configured to send a register read command and an address to all the data buffer circuits, and the data buffer circuits are configured to return data on the first data communications link between the host and the data buffer circuits.

2. The system of claim 1, wherein the command received from the host distinguishes between a register access operation and a memory device access operation.

3. The system of claim 1, wherein the communications link is a high speed serial interface and the first data communications link is a high speed serial interface, and the system is configured so that data from register operations are transferred on the high speed serial interfaces between the host and at least one of the group consisting of the memory control circuit, one or more of the at least one data buffer circuits, and both the memory control circuit and one or more of the at least one data buffer circuits.

4. The system of claim 1, wherein the system is configured to send a register access command and an address from the host to the memory control circuit and the address attached to any register access command distinguishes between memory control circuit register operations and data buffer circuit register operations.

5. The system of claim 1, wherein the communications link between the host and the memory control circuit is a high speed serial interface, and system is configured so that data transferred from memory control circuit register access operations is transferred over the high speed serial interface between the host and the memory control circuit.

6. The system of claim 1, wherein the system is configured so that write operations to the memory control circuit registers are targeted register writes, where write data, a register write command and an address are sent from the host to the memory control circuit in one packet over the communications link.

7. The system of claim 1, wherein the system comprises a plurality of data buffer circuits, and the system is configured for data buffer circuit register write operations wherein a register write command, a register address and a circuit identification are sent over the control communications link.

8. The system of claim 7, wherein the system is configured for data buffer circuit register write operations wherein the circuit identification is set to a broadcast value, and all data buffer circuits process the register write command, and wherein the system is further configured so that data is sent from the host directly to the plurality of data buffer circuits over the first data communications link.

9. The system of claim 7, wherein the system is configured for data buffer circuit targeted register write operations wherein the register write command, register address, circuit identification and data to be written to the specified data buffer circuit is sent to all the data buffer circuits over the control communications link, wherein the system is further configured so that only the data buffer circuit whose circuit identification matches the circuit identification sent over the control communications link processes the register write command.

10. The system of claim 7, wherein the system is configured to assign circuit identifications during system initialization.

11. A memory system for reading and writing data to and from circuit registers, the system comprising:

at least one memory control circuit configured to receive commands from a host and to output command and control signals;

at least one memory device configured to store data;

at least one data buffer circuit associated with the at least one memory control circuit and the at least one memory device, the data buffer circuit having data buffers and at least one register;

a first data communications link for communicating data between the host and the at least one data buffer circuit, and a second data communications link between the at least one data buffer circuit and the at least one memory device, wherein the first data communications link is a high speed serial interface;

a communications link between the host and the at least one memory control circuit, wherein the communications link is a high speed serial interface;

a control communications link between the at least one memory control circuit, and the at least one data buffer circuit for transmitting signals of the memory system;

wherein the system is configured so that data from register access operations is transferred over the high speed serial interfaces between the host and at least one of the group consisting of the memory control circuit, one or more of the data buffer circuits, and both the memory control circuit and one or more of the data buffer circuits, and

wherein the system is configured to send a register command and a register address from the host to the at least one memory control circuit, and the register address attached to any register command distinguishes between the at least one memory control circuit register operations and the at least one data buffer circuit register operations, and the system is further configured so that data transferred during the at least one memory control circuit register access operations is transferred over the communications link between the host and the at least one memory control circuit.

12. A memory system for storing data in response to a command received from a host, the memory system comprising:

a memory control circuit having a scheduler and at least one register, the memory control circuit configured to receive commands from the host and to output command and control signals;

at least one memory device configured to store data;

at least one data buffer circuit associated with the at least one memory device and the memory control circuit, the data buffer circuit having data buffers and at least one register associated therewith;

a communications link for communicating between the host and the at least one memory control circuit;

a first data communications link between the host and the at least one data buffer circuit, and a second data communications link between the at least one data buffer circuit and the at least one memory device; and

a control communications link between the memory control circuit and the at least one data buffer circuit,

wherein the system is configured so that register access commands are sent by the host to the memory control circuit over the communications link between the host and the memory control circuit, and

wherein the system is configured to send a register command and an address from the host to the memory control circuit and the address attached to any register command distinguishes between memory control circuit register operations and data buffer circuit register operations.

13. The system of claim 12, wherein the command received from the host distinguishes between a register access operation and a memory device access operation.

14. The system of claim 12, wherein the communications link is a high speed serial interface and the first data communications link is a high speed serial interface, and the system is configured so that data from register operations are transferred on the high speed serial interfaces between the host and at least one of the group consisting of the memory control circuit, one or more of the at least one data buffer circuits, and both the memory control circuit and one or more of the at least one data buffer circuits.

15. The system of claim 12, wherein the communications link between the host and the memory control circuit is a high speed serial interface, and system is configured so that data transferred from memory control circuit register access operations is transferred over the high speed serial interface between the host and the memory control circuit.

16. The system of claim 12, wherein the system is configured so that write operations to the memory control circuit registers are targeted register writes, where write data, a register write command and an address are sent from the host to the memory control circuit in one packet over the communications link.

17. The system of claim 12, wherein the system comprises a plurality of data buffer circuits, and the system is configured for data buffer circuit register write operations wherein a register write command, a register address and a circuit identification are sent over the control communications link.

18. The system of claim 17, wherein the system is configured for data buffer circuit register write operations wherein the circuit identification is set to a broadcast value, and all data buffer circuits process the register write command, and wherein the system is further configured so that data is sent from the host directly to the plurality of data buffer circuits over the first data communications link.

19. The system of claim 17, wherein the system is configured for data buffer circuit targeted register write operations wherein the register write command, register address, circuit identification and data to be written to the specified data buffer circuit is sent to all the data buffer circuits over the control communications link, wherein the system is further configured so that only the data buffer circuit whose circuit identification matches the circuit identification sent over the control communications link processes the register write command.

20. The system of claim 17, wherein the system is configured to assign circuit identifications during system initialization.