Register access in a distributed memory buffer system
First Claim
1. A memory system for storing data in response to a command received from a host, the memory system comprising:
- a memory control circuit having a scheduler and at least one register, the memory control circuit configured to receive commands from the host and to output command and control signals;
at least one memory device configured to store data;
at least one data buffer circuit associated with the at least one memory device and the memory control circuit, the data buffer circuit having data buffers and at least one register associated therewith;
a communications link for communicating between the host and the at least one memory control circuit;
a first data communications link between the host and the at least one data buffer circuit, and a second data communications link between the at least one data buffer circuit and the at least one memory device; and
a control communications link between the memory control circuit and the at least one data buffer circuit,wherein the system is configured so that register access commands are sent by the host to the memory control circuit over the communications link between the host and the memory control circuit, andwherein the system comprises a plurality of data buffer circuits configured as at least one of a rank, a channel, or both, wherein the memory control circuit is configured to send a register read command and an address to all the data buffer circuits, and the data buffer circuits are configured to return data on the first data communications link between the host and the data buffer circuits.
1 Assignment
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Accused Products
Abstract
A memory system, architecture, and method for storing data in response to commands received from a host is disclosed. The memory system includes a memory control circuit configured to receive commands from the host; at least one memory device configured to store data; and at least one data buffer circuit associated with the at least one memory device and the memory control circuit, the data buffer circuit having data buffers and at least one register. The system preferably includes communication links between the host, the at least one memory control circuit, the at least one data buffer circuit, and the at least one memory device. The system preferably is configured so that register access commands are sent by the host to the memory control circuit over the communication links between the host and the memory control circuit.
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Citations
20 Claims
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1. A memory system for storing data in response to a command received from a host, the memory system comprising:
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a memory control circuit having a scheduler and at least one register, the memory control circuit configured to receive commands from the host and to output command and control signals; at least one memory device configured to store data; at least one data buffer circuit associated with the at least one memory device and the memory control circuit, the data buffer circuit having data buffers and at least one register associated therewith; a communications link for communicating between the host and the at least one memory control circuit; a first data communications link between the host and the at least one data buffer circuit, and a second data communications link between the at least one data buffer circuit and the at least one memory device; and a control communications link between the memory control circuit and the at least one data buffer circuit, wherein the system is configured so that register access commands are sent by the host to the memory control circuit over the communications link between the host and the memory control circuit, and wherein the system comprises a plurality of data buffer circuits configured as at least one of a rank, a channel, or both, wherein the memory control circuit is configured to send a register read command and an address to all the data buffer circuits, and the data buffer circuits are configured to return data on the first data communications link between the host and the data buffer circuits. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A memory system for reading and writing data to and from circuit registers, the system comprising:
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at least one memory control circuit configured to receive commands from a host and to output command and control signals; at least one memory device configured to store data; at least one data buffer circuit associated with the at least one memory control circuit and the at least one memory device, the data buffer circuit having data buffers and at least one register; a first data communications link for communicating data between the host and the at least one data buffer circuit, and a second data communications link between the at least one data buffer circuit and the at least one memory device, wherein the first data communications link is a high speed serial interface; a communications link between the host and the at least one memory control circuit, wherein the communications link is a high speed serial interface; a control communications link between the at least one memory control circuit, and the at least one data buffer circuit for transmitting signals of the memory system; wherein the system is configured so that data from register access operations is transferred over the high speed serial interfaces between the host and at least one of the group consisting of the memory control circuit, one or more of the data buffer circuits, and both the memory control circuit and one or more of the data buffer circuits, and wherein the system is configured to send a register command and a register address from the host to the at least one memory control circuit, and the register address attached to any register command distinguishes between the at least one memory control circuit register operations and the at least one data buffer circuit register operations, and the system is further configured so that data transferred during the at least one memory control circuit register access operations is transferred over the communications link between the host and the at least one memory control circuit.
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12. A memory system for storing data in response to a command received from a host, the memory system comprising:
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a memory control circuit having a scheduler and at least one register, the memory control circuit configured to receive commands from the host and to output command and control signals; at least one memory device configured to store data; at least one data buffer circuit associated with the at least one memory device and the memory control circuit, the data buffer circuit having data buffers and at least one register associated therewith; a communications link for communicating between the host and the at least one memory control circuit; a first data communications link between the host and the at least one data buffer circuit, and a second data communications link between the at least one data buffer circuit and the at least one memory device; and a control communications link between the memory control circuit and the at least one data buffer circuit, wherein the system is configured so that register access commands are sent by the host to the memory control circuit over the communications link between the host and the memory control circuit, and wherein the system is configured to send a register command and an address from the host to the memory control circuit and the address attached to any register command distinguishes between memory control circuit register operations and data buffer circuit register operations. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20)
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Specification