×

Semiconductor memory

  • US 10,642,537 B2
  • Filed: 08/30/2018
  • Issued: 05/05/2020
  • Est. Priority Date: 11/30/2017
  • Status: Active Grant
First Claim
Patent Images

1. A semiconductor memory comprising:

  • a first plane that includes a first memory cell array;

    a second plane that includes a second memory cell array; and

    a control circuit that includes a first circuit configured to store a first priority for a first operation performed on the first plane, a second circuit configured to store a second priority for a second operation performed on the second plane, a first sequencer circuit for the first plane, and a second sequencer circuit for the second plane, and is configured to control the first and second operations based on the first priority and the second priority,wherein when a value of the second priority is higher than a value of the first priority, the second sequencer circuit outputs a first signal that indicates a start of a second process executed in the second operation, and the first sequencer circuit controls a start timing of a first process executed in the first operation based on the first signal, such that a timing of the first process executed in the first operation is delayed so as to not overlap with a timing of the second process executed in the second operation.

View all claims
  • 4 Assignments
Timeline View
Assignment View
    ×
    ×