Semiconductor memory
First Claim
1. A semiconductor memory comprising:
- a first plane that includes a first memory cell array;
a second plane that includes a second memory cell array; and
a control circuit that includes a first circuit configured to store a first priority for a first operation performed on the first plane, a second circuit configured to store a second priority for a second operation performed on the second plane, a first sequencer circuit for the first plane, and a second sequencer circuit for the second plane, and is configured to control the first and second operations based on the first priority and the second priority,wherein when a value of the second priority is higher than a value of the first priority, the second sequencer circuit outputs a first signal that indicates a start of a second process executed in the second operation, and the first sequencer circuit controls a start timing of a first process executed in the first operation based on the first signal, such that a timing of the first process executed in the first operation is delayed so as to not overlap with a timing of the second process executed in the second operation.
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Accused Products
Abstract
A semiconductor memory includes a first plane that includes a first memory cell array, a second plane that includes a second memory cell array, and a control circuit that includes a first circuit configured to store a first priority for a first operation performed on the first plane and a second circuit configured to store a second priority for a second operation performed on the second plane, and is configured to control the first and second operations based on the first priority and the second priority. When a value of the second priority is higher than a value of the first priority, the control circuit controls the first operation such that a timing of a process executed in the first operation does not overlap with a timing of a process executed in the second operation.
10 Citations
17 Claims
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1. A semiconductor memory comprising:
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a first plane that includes a first memory cell array; a second plane that includes a second memory cell array; and a control circuit that includes a first circuit configured to store a first priority for a first operation performed on the first plane, a second circuit configured to store a second priority for a second operation performed on the second plane, a first sequencer circuit for the first plane, and a second sequencer circuit for the second plane, and is configured to control the first and second operations based on the first priority and the second priority, wherein when a value of the second priority is higher than a value of the first priority, the second sequencer circuit outputs a first signal that indicates a start of a second process executed in the second operation, and the first sequencer circuit controls a start timing of a first process executed in the first operation based on the first signal, such that a timing of the first process executed in the first operation is delayed so as to not overlap with a timing of the second process executed in the second operation. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A memory system comprising:
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a controller; and a semiconductor memory including a first plane of memory cells, a second plane of memory cells, and a control circuit that includes a first circuit configured to store a first priority for a first operation performed on the first plane in response to a first command from the controller, a second circuit configured to store a second priority for a second operation performed on the second plane in response to a second command from the controller, a first sequencer circuit for the first plane, and a second sequencer circuit for the second plane, wherein the controller is configured to control the first and second operations based on the first priority and the second priority, wherein when a value of the second priority is higher than a value of the first priority, the second sequencer circuit outputs a first signal that indicates a start of a second process executed in the second operation, and the first sequencer circuit controls a start timing of a first process executed in the first operation based on the first signal, such that a timing of the first process executed in the first operation is delayed so as to not overlap with a timing of the second process executed in the second operation. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A method of performing parallel operations in a semiconductor memory including a first plane of memory cells, a second plane of memory cells, and a control circuit that includes a first circuit configured to store a first priority for a first process of a first operation performed on the first plane and a second circuit configured to store a second priority for a second process of a second operation performed on the second plane, said method comprising:
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determining that an amount of current consumption by the first and second processes exceeds a threshold; and when the amount of current consumption by the first and second processes exceeds the threshold, controlling the first and second operations based on the first priority and the second priority, wherein when a value of the second priority is higher than a value of the first priority, a timing of the first process executed in the first operation is delayed so as to not overlap with a timing of the second process executed in the second operation. - View Dependent Claims (14, 15, 16, 17)
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Specification