Multi-channel memory interface

• US 10,642,538 B1
• Filed: 09/28/2018
• Issued: 05/05/2020
• Est. Priority Date: 09/28/2018
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: MacLaren, John M., Earl, Jeffrey S., Hughes, Anne
• Primary Examiner(s): Siddique, Mushfique
• Application Number:
  US16/146,052
• Time in Patent Office: 585 Days
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0683 Plurality of storage devices
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/3308 using simulation
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1012 Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

Various embodiments provide for a multi-channel memory interface capable of supporting a multi-channel memory module (e.g., DIMM) that combines different memory types, such as DDR4/DDR5, DDR5/LPDDR5, or LPDDR4/LPDDR5, through a single physical layer (PHY) interface.

Claims

1. A circuit comprising:

a physical layer interface to couple to a memory physical layer;

a first memory controller interface to couple to a first memory controller that supports a first memory type channel, a second memory type channel, and a first maximum data width;

a second memory controller interface to couple to a second memory controller that supports at least the first memory type channel, and supports a second maximum data width that is less than or equal to the first maximum data width;

multiplexer logic to demultiplex one or more data signals from at least one of the first memory controller interface or the second memory controller interface to the physical layer interface, and to multiplex one or more data signals from the physical layer interface to at least one of the first memory controller interface or the second memory controller interface; and

signal handler logic to receive a first set of memory protocol signals from the first memory controller, receive a second set of memory protocol signals from the second memory controller, generate a third set of memory protocol signals based on the first set of memory protocol signals and the second set of memory protocol signals, and provide the third set of memory protocol signals for transmission to the memory physical layer through the physical layer interface.

2. The circuit of claim 1, wherein the signal handler logic generates the third set of memory protocol signals based on the first set of memory protocol signals and the second set of memory protocol signals by at least one of:

logically OR a first reset signal from the first set of memory protocol signals and a second reset signal from the second set of memory protocol signals to generate a reset signal in the third set of memory protocol signals;

or

multiplexing the first reset signal and the second reset signal, based on whether one of the first memory controller and the second memory controller is set as a master memory controller, to generate the reset signal in the third set of memory protocol signals.

3. The circuit of claim 1, wherein the signal handler logic generates the third set of memory protocol signals based on the first set of memory protocol signals and the second set of memory protocol signals such that:

each of the first memory controller and the second memory controller has an independent programming path to the memory physical layer through the physical layer interface; and

one of the first memory controller and the second memory controller is set as a memory master controller.

4. The circuit of claim 1, wherein the signal handler logic generates the third set of memory protocol signals based on the first set of memory protocol signals and the second set of memory protocol signals by:

determining whether the first memory controller is asserting an initialization start signal in the first set of memory protocol signals and the second memory controller is asserting the initialization start signal in the second set of memory protocol signals; and

asserting the initialization start signal in the third set of memory protocol signals based on determining that both the first memory controller is asserting the initialization start signal in the first set of memory protocol signals and the second memory controller is asserting the initialization start signal in the second set of memory protocol signals.

5. The circuit of claim 1, wherein the signal handler logic generates the third set of memory protocol signals based on the first set of memory protocol signals and the second set of memory protocol signals by:

determining whether the first memory controller is asserting a clock disable signal in the first set of memory protocol signals and the second memory controller is asserting the clock disable signal in the second set of memory protocol signals; and

asserting the initialization start signal in the third set of memory protocol signals based on determining that both the first memory controller is asserting the clock disable signal in the first set of memory protocol signals and the second memory controller is asserting the clock disable signal in the second set of memory protocol signals.

6. The circuit of claim 1, wherein the signal handler logic is to further receive through the physical layer interface a fourth set of memory protocol signals from the memory physical layer, and selectively pass the fourth set of memory protocol signals to at least one of the first memory controller through the first memory controller interface or the second memory controller through the second memory controller interface.

7. The circuit of claim 6, wherein the signal handler logic selectively passes the fourth set of memory protocol signals to at least one of the first memory controller or the second memory controller by passing an initialization complete signal, included in the fourth set of memory protocol signals, to both the first memory controller and the second memory controller.

8. The circuit of claim 6, wherein the signal handler logic selectively passes the fourth set of memory protocol signals to at least one of the first memory controller or the second memory controller by passing a request, included in the fourth set of memory protocol signals, to both the first memory controller and the second memory controller, and wherein the signal handler logic generates the third set of memory protocol signals based on the first set of memory protocol signals and the second set of memory protocol signals by:

detecting for an acknowledgement to the request from each of the first memory controller and the second memory controller; and

in response to detecting the acknowledgement from each of the first memory controller and the second memory controller, passing the acknowledgement to the memory physical layer through the physical layer interface.

9. The circuit of claim 8, wherein the request comprises at least one of a physical layer master request or a physical layer update request.

10. The circuit of claim 6, wherein the signal handler logic selectively passes the fourth set of memory protocol signals to at least one of the first memory controller or the second memory controller by passing a bus error signal, included in the fourth set of memory protocol signals, to both the first memory controller and the second memory controller.

11. The circuit of claim 1, further comprising data frequency selection logic to:

assert a hardware interface request to both the first memory controller and the second memory controller;

detect for an acknowledgement to the hardware interface request from each of the first memory controller and the second memory controller; and

in response to detecting the acknowledgement from each of the first memory controller and the second memory controller, send a data frequency selection command to both the first memory controller and the second memory controller.

12. The circuit of claim 1, further comprising the first memory controller and the second memory controller.

13. The circuit of claim 12, wherein each of the first memory controller and the second memory controller comprises oscillator logic to:

detect receipt of a request from the memory physical layer through the physical layer interface; and

in response to detecting receipt of the request;

determine whether an oscillator-related function is in progress with respect to a memory channel associated with the memory physical layer; and

in response to determining that the oscillator-related function is in progress;

detect when the oscillator-related function is no longer in progress; and

in response to detecting that the oscillator-related function is no longer in progress, send an acknowledgment of the request to the memory physical layer through the physical layer interface.

14. The circuit of claim 1, wherein the first memory type channel comprises a memory channel for double data rate fifth-generation (DDR5) and the second memory type channel comprises a memory channel for double data rate fourth-generation (DDR4).

15. The circuit of claim 1, wherein the physical layer interface comprises a DDR PHY Interface (DFI) with flops.

16. The circuit of claim 1, wherein at least one of the first memory controller or the second memory controller comprises a DDR PHY Interface (DFI) with no flops.

17. A method comprising:

receiving, at a first memory controller interface of a memory channel interface, a first set of data signals from a first memory controller coupled to the first memory controller interface, the first memory controller supporting a first memory type channel, a second memory type channel, and a first maximum data width;

receiving, at a second memory controller interface of the memory channel interface, a second set of data signals from a second memory controller coupled to the second memory controller interface, the second memory controller supporting at least the first memory type channel and supporting a second maximum data width that is less than or equal to than the first maximum data width;

demultiplexing, by the memory channel interface, one or more data signals from the first set of data signals or the second set of data signals to a physical layer interface of the memory channel interface, the physical layer interface being coupled to a memory physical layer;

multiplexing, by the memory channel interface, one or more data signals from the physical layer interface to at least one of the first memory controller interface or the second memory controller interface;

receiving, by the memory channel interface, a first set of memory protocol signals from the first memory controller interface;

receiving, by the memory channel interface, a second set of memory protocol signals from the second memory controller interface;

generating, by the memory channel interface, a third set of memory protocol signals based on the first set of memory protocol signals and the second set of memory protocol signals; and

sending, by the memory channel interface, the third set of memory protocol signals to the physical layer interface.