Machine perception and dense algorithm integrated circuit
First Claim
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1. An integrated circuit comprising:
- a plurality of array cores, each array core of the plurality of array cores comprising;
a plurality of distinct data processing circuits, at least one of the plurality of distinct data processing circuits being arranged along each interior side of each array core; and
a data queue register file;
wherein;
a combination of the plurality of array cores define an integrated circuit array;
a first plurality of dual FIFOs that load data into the integrated circuit array on a first-in, first-out basis, such that an oldest dataset entering a respective dual FIFO of the first plurality of dual FIFOs is first disposed by the respective dual FIFO,wherein the first plurality of dual FIFOs are arranged along a first peripheral side of the integrated circuit array;
a second plurality of dual FIFOs that load data into the integrated circuit array on a first-in, first-out basis, such that an oldest dataset entering a respective dual FIFO of the second plurality of dual FIFOs is first disposed by the respective dual FIFO, wherein the second plurality of dual FIFOs are arranged along a second peripheral side of the integrated circuit array that is distinct from the first peripheral side of the integrated circuit array.
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Abstract
A circuit that includes a plurality of array cores, each array core of the plurality of array cores comprising: a plurality of distinct data processing circuits; and a data queue register file; a plurality of border cores, each border core of the plurality of border cores comprising: at least a register file, wherein: [i] at least a subset of the plurality of border cores encompasses a periphery of a first subset of the plurality of array cores; and [ii] a combination of the plurality of array cores and the plurality of border cores define an integrated circuit array.
33 Citations
19 Claims
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1. An integrated circuit comprising:
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a plurality of array cores, each array core of the plurality of array cores comprising; a plurality of distinct data processing circuits, at least one of the plurality of distinct data processing circuits being arranged along each interior side of each array core; and a data queue register file; wherein; a combination of the plurality of array cores define an integrated circuit array; a first plurality of dual FIFOs that load data into the integrated circuit array on a first-in, first-out basis, such that an oldest dataset entering a respective dual FIFO of the first plurality of dual FIFOs is first disposed by the respective dual FIFO, wherein the first plurality of dual FIFOs are arranged along a first peripheral side of the integrated circuit array; a second plurality of dual FIFOs that load data into the integrated circuit array on a first-in, first-out basis, such that an oldest dataset entering a respective dual FIFO of the second plurality of dual FIFOs is first disposed by the respective dual FIFO, wherein the second plurality of dual FIFOs are arranged along a second peripheral side of the integrated circuit array that is distinct from the first peripheral side of the integrated circuit array. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 18, 19)
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16. An integrated circuit comprising:
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a plurality of array cores, each array core of the plurality of array cores comprising; a plurality of distinct data processing circuits, at least one of the plurality of distinct data processing circuits being arranged along each interior side of each array core; and a data queue register file; wherein; a combination of the plurality of array cores define an integrated circuit array; a plurality of border cores, each border core of the plurality of border cores comprising; at least a register file, wherein; [i] a combination of the plurality of array cores and the plurality of border cores define the integrated circuit array; and [ii] a subset of the plurality of border cores define one or more peripheral sides of the integrated circuit array; a dispatch controller that provides; (i) data movement instructions that causes an automatic movement of data;
(a) between a hierarchical memory structure of the integrated circuit and the integrated circuit array;
(b) within each respective array core of the plurality of array cores;
(c) between respective array cores and between array cores and border cores of the integrated circuit array; and(ii) computation instructions that define a plurality of computations to be executed by the plurality of array cores of the integrated circuit array.
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17. An integrated circuit comprising:
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a plurality of array cores, each array core of the plurality of array cores comprising; a plurality of distinct data processing circuits, at least one of the plurality of distinct data processing circuits being arranged along each interior side of each array core; and a data queue register file; wherein; a combination of the plurality of array cores define an integrated circuit array; a plurality of border cores, each border core of the plurality of border cores comprising; at least a register file, wherein; [i] a combination of the plurality of array cores and the plurality of border cores define the integrated circuit array; and [ii] a subset of the plurality of border cores define one or more peripheral sides of the integrated circuit array; a dispatch controller that provides data movement instructions, wherein the data movement instructions comprise a data flow schedule that; (i) defines an automatic movement of data within the integrated circuits; and (ii) sets one or more border cores of the plurality of border cores to a predetermined constant value if no data is provided to the one or more border cores according to the predetermined data flow schedule, wherein the data flow schedule comprises a schedule of memory addresses executable by one or more of a plurality of periphery load stores.
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Specification